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CA3304D データシート(PDF) 4 Page - Intersil Corporation |
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CA3304D データシート(HTML) 4 Page - Intersil Corporation |
4 / 11 page 4-10 Pin Descriptions PIN NUMBER NAME DESCRIPTION 1 Bit 1 Bit 1 (LSB). Output Data Bits (High = True) 2 Bit 2 Bit 2. 3 Bit 3 Bit 3. 4 Bit 4 Bit 4 (MSB). 5 DC Data Change. 6 OF Overflow. 7 CE2 Three-State Output Enable Input, active low. See the Chip Enable Truth Table. 8VSS Digital Ground. 9 CE1 Three-State Output Enable Input, active high. See the Chip Enable Truth Table. 10 VAA+ Analog Power Supply, +5V. 11 VIN Analog Signal Input. 12 VREF+ Reference Voltage Positive Input. 13 VREF- Reference Voltage Negative Input. 14 VAA- Analog Ground. 15 CLK Clock Input. 16 VDD Digital Power Supply, +5V. CHIP ENABLE TRUTH TABLE CE1 CE2 BIT 1 - BIT 4 DC, OF 0 1 Valid Valid 1 1 Three-State Valid X 0 Three-State Three-State X = Don't Care TABLE 1. OUTPUT CODE TABLE CODE DESCRIPTION INPUT VOLTAGE (V) OUTPUT CODE DECIMAL COUNT VREF+ = 1V VREF- = -1V 1.6V 0V 2V 0V 3.2V 0V 4.8V 0V OF B4 B3 B2 B1 Zero -1.000 0 0 0 0 00000 0 1 LSB -0.875 0.1 0.125 0.2 0.3 00001 1 2 LSB -0.750 0.2 0.250 0.4 0.6 00010 2 • • • • • • ••••• • • • • • • • ••••• • • • • • • • ••••• • • • • • • • ••••• • 1/ 2 Full Scale -1 LSB -0.125 0.7 0.875 1.4 2.1 00111 7 1/ 2 Full Scale 0 0.8 1.000 1.6 2.4 01000 8 1/ 2 Full Scale +1 LSB 0.125 0.9 1.125 1.8 2.7 01001 9 • • • • • • ••••• • • • • • • • ••••• • • • • • • • ••••• • • • • • • • ••••• • Full Scale -1 LSB 0.750 1.4 1.750 2.8 4.2 01110 14 Full Scale 0.875 1.5 1.875 3.0 4.5 01111 15 Overflow 1.000 1.6 2.000 3.2 4.8 11111 31 Step Size 0.125 0.1 0.125 0.2 0.3 NOTE: 1. The voltages listed are the ideal centers of each output code shown as a function of its associated reference voltage See Ideal Transfer Curve Figure 6. The output code should exist for an input equal to the ideal center voltage ±1/2 of the step size. CA3304, CA3304A |
同様の部品番号 - CA3304D |
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同様の説明 - CA3304D |
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