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CD22357AE データシート(PDF) 7 Page - Harris Corporation

部品番号 CD22357AE
部品情報  CMOS Single-Chip, Full-Feature PCM CODEC
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メーカー  HARRIS [Harris Corporation]
ホームページ  http://www.harris.com
Logo HARRIS - Harris Corporation

CD22357AE データシート(HTML) 7 Page - Harris Corporation

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CD22354A, CD22357A
Hold Time from 3rd Period of Bit
Clock Low to Frame Sync
(FSX or FSR)
tHBFI
Long Frame Sync Pulse
(from 3 to 8-Bit Clock Periods Long)
100
-
-
ns
Minimum Width of the Frame
Sync Pulse (Low Level)
tWFL
64K Bit/s Operating Mode
160
-
-
ns
NOTE:
1. For short frame sync timing, FSX and FSR must go high while their respective bit clocks are high.
Pin Descriptions
PIN NO.
SYMBOL
DESCRIPTION
1
V-
Negative power supply, V- = -5V
±5%.
2
GND
Analog and digital ground. All signals referenced to this pin.
3VFRO
Analog output of RECEIVE FILTER.
4
V+
Positive power supply, V+ = 5V
±5%.
5FSR
Receive Frame Sync Pulse which enables BCLKR to shift PCM data into DR. FSR is an 8kHz PULSE
TRAIN.
6DR
Receive Data Input. PCM data is shifted into DR following the FSR leading edge.
7
BCLKR/CLK-
SEL
The Receive Bit Clock, which shifts data into DR after the frame sync leading edge, may vary from 64kHz
to 2.048MHz. Alternatively, the leading edge may be a logic input which selects either 1.536MHz/
1.544MHz or 2.048MHz for Master Clock in synchronous mode and BCLKX is used for both transmit and
receive directions.
8
MCLKR/PDN
Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLKX,
but best performance is realized from synchronous operation. When this pin is continuously connected
low, MCLKX is selected for all internal timing. When this pin is continuously connected high, the device is
powered down.
9
MCLKX
Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLKR,
but best performance is realized from synchronous operation.
10
BCLKX
The Bit Clock which shifts out the PCM Data on DX. May vary from 64kHz to 2.048MHz, but must be syn-
chronous with MCLKX.
11
DX
The THREE-STATE PCM Data Output which is enabled by FSX.
12
FSX
Transmit Frame Sync Pulse input which enables BCLKX to shift out the data on DX. FSX is an 8kHz
PULSE TRAIN.
13
TSX
Open drain output which pulses low during the encoder time slot.
14
GSX
Transmit gain adjust.
15
VFXI-
Inverting input of the transmit input amplifier.
16
VFXI+
Non-inverting input of the transmit input amplifier.
Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS


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