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CD40105 データシート(PDF) 2 Page - Intersil Corporation |
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CD40105 データシート(HTML) 2 Page - Intersil Corporation |
2 / 10 page 7-1318 CD40105BMS Unloading Data - As soon as the first word has rippled to the output, DATA-OUT READY (DOR) goes high, and data can be removed by a falling edge on the SO input. This fall- ing edge causes the DOR signal to go low while the word on the output is dumped and the next word moves to the output. As long as valid data are available in the FIFO, the DOR sig- nal will go high again signifying that the next word is ready at the output. When the FIFO is empty, DOR will remain low, and any further commands will be ignored until a “1” marker ripples down to the last control register, when DOR goes high. Unloading of data is inhibited while the 3-state control input is high. The 3-state control signal should not be shifted from high to low (data outputs turned on) while the SHIFT- OUT is at logic 0. This level change would cause the first word to be shifted out (unloaded) immediately and the data to be lost. Cascading - The CD40105BMS can be cascaded to form longer registers simply by connecting the DIR to SO and DOR to SI. In the cascaded mode, a MASTER RESET pulse must be applied after the supply voltage is turned on. For words wider than 4 bits, the DIR and the DOR outputs must be gated together with AND gates. Their outputs drive the SI and SO inputs in parallel, if expanding is done in both direc- tions (see Figures 9 and 11). 3-State Outputs - In order to facilitate data busing, 3-state outputs are provided on the data output lines, while the load condition of the register can be detected by the state of the DOR output. Master Reset - A high on the MASTER RESET (MR) sets all the control logic marker bits to “0”. DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be superseded when the first word is loaded. The shift-in must be low during Mas- ter Reset. The CD40105BMS is supplied in these 16-lead outline pack- ages: Braze Seal DIP H4X Frit Seal DIP H1F Ceramic Flatpack H6W Logic Diagram CL CL 2 15 1 9 3 4 5 6 7 R SQ R SQ Q 1 R SQ Q 2 4 - 15 R SQ Q 16 R SQ CL 4 LATCHES CL CL 4 LATCHES CL CL 4 LATCHES CL CL 4 LATCHES CL 3 STATE OUTPUT BUFFERS 13 12 11 10 * * * * * * *ALL INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK POS 1 POS 2 POS 3 POS 16 MASTER RESET SHIFT IN D0 D1 D2 D3 DATA IN READY (DIR) SHIFT OUT 3 - STATE CONTROL (OUTPUT ENABLE) DATA READY (DOR) Q0 Q1 Q2 Q3 ** VDD VSS p n CL CL p n DETAIL OF LATCHES 14 |
同様の部品番号 - CD40105 |
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同様の説明 - CD40105 |
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