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AD7866 データシート(PDF) 4 Page - Analog Devices

部品番号 AD7866
部品情報  Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD7866 データシート(HTML) 4 Page - Analog Devices

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REV. A
–4–
AD7866
TIMING SPECIFICATIONS1(V
DD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)
Limit at
Parameter
TMIN, TMAX
Unit
Description
fSCLK
2
10
kHz min
20
MHz max
tCONVERT
16
tSCLK
ns max
tSCLK = 1/fSCLK
800
ns max
fSCLK = 20 MHz
tQUIET
50
ns max
Minimum Time between End of Serial Read and Next Falling Edge of
CS
t2
10
ns min
CS to SCLK Setup Time
t3
3
25
ns max
Delay from
CS until D
OUTA and DOUTB Three-State Disabled
t4
3
40
ns max
Data Access Time after SCLK Falling Edge. VDRIVE
3 V, CL = 50 pF;
VDRIVE < 3 V, CL = 25 pF
t5
0.4 tSCLK
ns min
SCLK Low Pulsewidth
t6
0.4 tSCLK
ns min
SCLK High Pulsewidth
t7
10
ns min
SCLK to Data Valid Hold Time
t8
4
25
ns max
CS Rising Edge to D
OUTA, DOUTB, High Impedance
t9
4
10
ns min
SCLK Falling Edge to DOUTA, DOUTB, High Impedance
50
ns max
SCLK Falling Edge to DOUTA, DOUTB, High Impedance
NOTES
1Sample tested at 25
°C to ensure compliance. All input signals are specified with t
R = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2Mark/Space ratio for the CLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4t
8, t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times t8 and t9 quoted in the timing characteristics are the true
bus relinquish times of the part and are independent of the bus loading.
Specifications subject to change without notice.
1.6V
200 AIOL
200 A
IOH
CL
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Digital Output Timing Specifications


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