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AD7940 データシート(PDF) 5 Page - Analog Devices |
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AD7940 データシート(HTML) 5 Page - Analog Devices |
5 / 20 page AD7940 Rev. A | Page 5 of 20 TIMING SPECIFICATIONS Sample tested at initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. VDD = 2.50 V to 5.5 V; TA = TMIN to TMAX, unless otherwise noted. Table 3. Limit at T MIN, TMAX Parameter 3 V 5 V Unit Description f SCLK 1 250 250 kHz min 2.5 2.5 MHz max t CONVERT 16 × t SCLK 16 × t SCLK min t QUIET 50 50 ns min Minimum quiet time required between bus relinquish and start of next conversion t 1 10 10 ns min Minimum CS pulse width t 2 10 10 ns min CS to SCLK setup time t 3 2 48 35 ns max Delay from CS until SDATA three-state disabled t 4 2 120 80 ns max Data access time after SCLK falling edge t 5 0.4 t SCLK 0.4 t SCLK ns min SCLK low pulse width t 6 0.4 t SCLK 0.4 t SCLK ns min SCLK high pulse width t 7 10 10 ns min SCLK to data valid hold time t 8 3 45 35 ns max SCLK falling edge to SDATA high impedance t POWER-UP 4 1 1 µs typ Power up time from full power-down 1 Mark/space ratio for the SCLK input is 40/60 to 60/40. 2 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 3 t 8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 4 See the Power vs. Throughput Rate section. 200 µA IOL 200 µA IOH 1.6V TO OUTPUT PIN CL 50pF Figure 2. Load Circuit for Digital Output Timing Specification |
同様の部品番号 - AD7940_15 |
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同様の説明 - AD7940_15 |
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