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AD9238 データシート(PDF) 6 Page - Analog Devices |
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AD9238 データシート(HTML) 6 Page - Analog Devices |
6 / 48 page AD9238 Rev. C | Page 6 of 48 DIGITAL SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 3. Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit LOGIC INPUTS High Level Input Voltage Full IV 2.0 2.0 2.0 V Low Level Input Voltage Full IV 0.8 0.8 0.8 V High Level Input Current Full IV −10 +10 −10 +10 −10 +10 μA Low Level Input Current Full IV −10 +10 −10 +10 −10 +10 μA Input Capacitance Full IV 2 2 2 pF LOGIC OUTPUTS1 High Level Output Voltage Full IV DRVDD − 0.05 DRVDD − 0.05 DRVDD − 0.05 V Low Level Output Voltage Full IV 0.05 0.05 0.05 V 1 Output voltage levels measured with capacitive load only on each output. SWITCHING SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 4. Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 20 40 65 MSPS Minimum Conversion Rate Full V 1 1 1 MSPS CLK Period Full V 50.0 25.0 15.4 ns CLK Pulse-Width High1 Full V 15.0 8.8 6.2 ns CLK Pulse-Width Low1 Full V 15.0 8.8 6.2 ns DATA OUTPUT PARAMETER Output Delay2 (tPD) Full VI 2 3.5 6 2 3.5 6 2 3.5 6 ns Pipeline Delay (Latency) Full V 7 7 7 Cycles Aperture Delay (tA) Full V 1.0 1.0 1.0 ns Aperture Uncertainty (tJ) Full V 0.5 0.5 0.5 ps rms Wake-Up Time3 Full V 2.5 2.5 2.5 ms OUT-OF-RANGE RECOVERY TIME Full V 2 2 2 Cycles 1 The AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24). 2 Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output. 3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB. N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 ANALOG INPUT CLOCK DATA OUT N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N MIN 2.0ns, MAX 6.0ns tPD = Figure 2. Timing Diagram |
同様の部品番号 - AD9238_15 |
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同様の説明 - AD9238_15 |
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