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AD14060L データシート(PDF) 6 Page - Analog Devices

部品番号 AD14060L
部品情報  DSP Multiprocessor Family
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD14060L データシート(HTML) 6 Page - Analog Devices

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AD14060/AD14060L
Rev. B | Page 6 of 48
Table 4. Reset
5 V
3.3 V
Parameter
Min
Max
Min
Max
Unit
Reset
Timing Requirements:
tWRST
RESET Pulse Width Low1
4 tCK
4 tCK
ns
tSRST
RESET Setup before CLKIN High2
14 + DT/2
tCK
14 + DT/2
tCK
ns
1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of the external clock oscillator).
2 Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (that is, for a SIMD system). Not required for
multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
CLKIN
RESET
tWRST
tSRST
Figure 3. Reset
Table 5. Interrupts
5 V
3.3 V
Parameter
Min
Max
Min
Max
Unit
Interrupts
Timing Requirements:
tSIR
IRQ2-0 Setup before CLKIN High1
18 + 3 DT/4
18 + 3 DT/4
ns
tHIR
IRQ2-0 Hold before CLKIN High1
11.5 + 3 DT/4
11.5 + 3 DT/4
ns
tIPW
IRQ2-0 Pulse Width2
2 + tCK
2 + tCK
ns
1 Only required for IRQx recognition in the following cycle.
2 Applies only if tSIR and tHIR requirements are not met.
CLKIN
IRQ2–0
tIPW
tHIR
tSIR
Figure 4. Interrupts


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