ADF4157_15 datasheet(3/24 Pages) AD

部品番号	ADF4157

部品情報	High Resolution 6 GHz Fractional-N Frequency Synthesizer

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Data Sheet

ADF4157

Rev. D | Page 3 of 24

SPECIFICATIONS

AVDD = DVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;

dBm referred to 50 Ω.

Table 1.

Parameter

B Version1

Unit

Test Conditions/Comments

RF CHARACTERISTICS (3 V)

RF Input Frequency (RFIN)

0.5/6.0

GHz min/max

−10 dBm/0 dBm min/max; for lower frequencies, ensure slew rate

(SR) > 400 V/µs

REFERENCE CHARACTERISTICS

REFIN Input Frequency

10/300

MHz min/max

For fREFIN < 10 MHz, ensure slew rate > 50 V/µs

REFIN Input Sensitivity

0.4/AVDD

V p-p min/max

For 10 MHz < fREFIN < 250 MHz, biased at AVDD/22

0.7/AVDD

V p-p min/max

For 250 MHz < fREFIN < 300 MHz, biased at AVDD/22

REFIN Input Capacitance

10

pF max

REFIN Input Current

±100

µA max

PHASE DETECTOR

Phase Detector Frequency3

32

MHz max

CHARGE PUMP

ICP Sink/Source

Programmable

High Value

5

mA typ

With RSET = 5.1 kΩ

Low Value

312.5

µA typ

Absolute Accuracy

2.5

% typ

With RSET = 5.1 kΩ

RSET Range

2.7/10

kΩ min/max

ICP Three-State Leakage Current

1

nA typ

Sink and source current

Matching

2

% typ

0.5 V < VCP < VP – 0.5

ICP vs. VCP

2

% typ

0.5 V < VCP < VP – 0.5

ICP vs. Temperature

2

% typ

VCP = VP/2

LOGIC INPUTS

VINH, Input High Voltage

1.4

V min

VINL, Input Low Voltage

0.6

V max

IINH/IINL, Input Current

±1

µA max

CIN, Input Capacitance

10

pF max

LOGIC OUTPUTS

VOH, Output High Voltage

1.4

V min

Open-drain 1 kΩ pull-up to 1.8 V

VOH, Output High Voltage

VDD – 0.4

V min

CMOS output chosen

VOL, Output Low Voltage

0.4

V max

IOL = 500 µA

POWER SUPPLIES

AVDD

2.7/3.3

V min/max

DVDD

AVDD

VP

AVDD/5.5

V min/V max

IDD

29

mA max

23 mA typical

Low Power Sleep Mode

10

µA typ

NOISE CHARACTERISTICS

Normalized Phase Noise Floor

(

PN

SYNTH)

4

−211

dBc/Hz typ

PLL loop B/W = 500 kHz;

measured at 100 kHz

Normalized 1/f Noise (PN1_f)5

−110

dBc/Hz typ

10 kHz offset; normalized to 1 GHz

Phase Noise Floor6

−137

dBc/Hz typ

@ 10 MHz PFD frequency

−133

dBc/Hz typ

@ 25 MHz PFD frequency

Phase Noise Performance7

@ VCO output

5800 MHz Output8

−87

dBc/Hz typ

@ 2 kHz offset, 25 MHz PFD frequency

1 Operating temperature of B version is −40°C to +85°C.

2 AC-coupling ensures AV

DD/2 bias.

3 Guaranteed by design. Sample tested to ensure compliance.

4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider

value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N).

5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, F

RF,

and at a frequency offset f is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

7 The phase noise is measured with the EV-ADF4157SD1Z and the Agilent E5052A phase noise system.

8 f

REFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 2 kHz; RFOUT = 5800.25 MHz; N = 232; loop bandwidth = 20 kHz.

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