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ADF4210 データシート(PDF) 10 Page - Analog Devices |
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ADF4210 データシート(HTML) 10 Page - Analog Devices |
10 / 20 page REV. A ADF4210/ADF4211/ADF4212/ADF4213 –10– PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 5 is a simplified schematic. The PFD includes a fixed-delay element that sets the width of the antibacklash pulse. This is typically 3 ns. This pulse ensures that there is no deadzone in the PFD transfer function and gives a consistent reference spur level. DELAY U3 CLR2 Q2 D2 U2 CLR1 Q1 D1 CHARGE PUMP DOWN UP HI HI U1 R DIVIDER N DIVIDER CP OUTPUT R DIVIDER N DIVIDER CP CPGND VP Figure 5. RF/IF PFD Simplified Schematic and Timing (In Lock) MUXOUT AND LOCK DETECT The output multiplexer on the ADF421x family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by P3, P4, P11, and P12. See Tables III and V. Figure 6 shows the MUXOUT section in block dia- gram form. DVDD MUXOUT DGND IF ANALOG LOCK DETECT IF R COUNTER OUTPUT IF N COUNTER OUTPUT IF/RF ANALOG LOCK DETECT RF R COUNTER OUTPUT RF N COUNTER OUTPUT RF ANALOG LOCK DETECT CONTROL MUX DIGITAL LOCK DETECT Figure 6. MUXOUT Circuit Lock Detect MUXOUT can be programmed for two types of lock detect: Digital Lock Detect and Analog Lock Detect. Digital Lock Detect is active high. It is set high when the phase error on three consecutive Phase Detector cycles is less than 15 ns. It will stay set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k Ω nominal. When lock has been detected, it is high with narrow low-going pulses. RF/IF INPUT SHIFT REGISTER The ADF421x family digital section includes a 24-bit input shift register, a 14-bit IF R counter and a 18-bit IF N counter, com- prising a 6-bit IF A counter and a 12-bit IF B counter. Also present is a 14-bit RF R counter and an 18-bit RF N counter, comprising a 6-bit RF A counter and a 12-bit RF B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs DB1, DB0 as shown in the timing diagram of Figure 1. The truth table for these bits is shown in Table VI. Table I shows a summary of how the latches are programmed. Table I. C2, C1 Truth Table Control Bits C2 C1 Data Latch 0 0 IF R Counter 0 1 IF AB Counter (A and B) 1 0 RF R Counter 1 1 RF AB Counter (A and B) |
同様の部品番号 - ADF4210_15 |
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同様の説明 - ADF4210_15 |
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