ADF7020-1_15 datasheet(6/48 Pages) AD

部品番号	ADF7020-1

部品情報	High Performance FSK/ASK Transceiver IC

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ADF7020-1

Rev. 0 | Page 6 of 48

Min

Typ

Max

Unit

Test Conditions

Parameter

PHASE-LOCKED LOOP

VCO Gain

40

MHz/V

433 MHz, VCO adjust = 0,

VCO_BIAS_SETTING = 2

35

MHz/V

315 MHz, VCO adjust = 0,

VCO_BIAS_SETTING = 2

16.5

MHz/V

135 MHz, VCO adjust = 0,

VCO_BIAS_SETTING = 1

Phase Noise (In-Band)

−89

dBc/Hz

PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz,

FRF = 315 MHz, VCO_BIAS_SETTING = 2

Normalized In-Band Phase Noise

Floor 9

−198

dBc/Hz

Phase Noise (Out-of-Band)

−110

dBc/Hz

1 MHz offset

Residual FM

128

Hz

From 200 Hz to 20 kHz, FRF = 315 MHz

PLL Settling

40

μs

Measured for a 10 MHz frequency step to

within 5 ppm accuracy, PFD = 20 MHz,

LBW = 50 kHz

REFERENCE INPUT

Crystal Reference

3.625

24

MHz

Must ensure PFD maximum is not exceeded

External Oscillator

3.625

24

MHz

Load Capacitance

33

pF

Refer to the crystal’s data sheet

Crystal Start-Up Time

2.1

ms

11.0592 MHz crystal, using 33 pF load

capacitors

1.0

ms

Using 16 pF load capacitors

Input Level

CMOS

levels

See the Reference Input section

ADC PARAMETERS

INL

±1

LSB

From 2.3 V to 3.6 V, TA = 25°C

DNL

±1

LSB

From 2.3 V to 3.6 V, TA = 25°C

TIMING INFORMATION

Chip Enabled to Regulator Ready

10

μs

CREG = 100 nF

Chip Enabled to RSSI Ready

3.0

ms

See Table 13 for more details

Tx-to-Rx Turnaround Time

150 μs +

(5 × TBIT)

Time to synchronized data out, includes

AGC settling. See AGC Information and

Timing section for more details.

LOGIC INPUTS

Input High Voltage, VINH

0.7 × V DD

V

Input Low Voltage, VINL

0.2 × V DD

V

Input Current, IINH/IINL

±1

μA

Input Capacitance, CIN

10

pF

Control Clock Input

50

MHz

LOGIC OUTPUTS

Output High Voltage, VOH

DVDD − 0.4

V

IOH = 500 μA

Output Low Voltage, VOL

0.4

V

IOL = 500 μA

CLKOUT Rise/Fall

5

ns

CLKOUT Load

10

pF

TEMPERATURE RANGE—TA

−40

+85

°C

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