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ADUM3401 データシート(PDF) 4 Page - Analog Devices |
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ADUM3401 データシート(HTML) 4 Page - Analog Devices |
4 / 24 page ADuM3400/ADuM3401/ADuM3402 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions SWITCHING SPECIFICATIONS ADuM340xARW Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 50 65 100 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 50 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching6 tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels ADuM340xBRW Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 20 32 50 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 15 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional Channels6 tPSKCD 3 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Opposing-Directional Channels6 tPSKOD 6 ns CL = 15 pF, CMOS signal levels ADuM340xCRW Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 18 27 32 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 10 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional Channels6 tPSKCD 2 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Opposing-Directional Channels6 tPSKOD 5 ns CL = 15 pF, CMOS signal levels For All Models Output Disable Propagation Delay (High/Low-to-High Impedance) tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels Output Enable Propagation Delay (High Impedance-to-High/Low) tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic High Output7 |CMH| 25 35 kV/µs VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V Common-Mode Transient Immunity at Logic Low Output7 |CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel8 IDDI (D) 0.20 mA/Mbps Output Dynamic Supply Current per Channel8 IDDO (D) 0.05 mA/Mbps Rev. C | Page 4 of 24 |
同様の部品番号 - ADUM3401_15 |
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同様の説明 - ADUM3401_15 |
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