データシートサーチシステム |
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ADV7178 データシート(PDF) 9 Page - Analog Devices |
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ADV7178 データシート(HTML) 9 Page - Analog Devices |
9 / 44 page ADV7177/ADV7178 Rev. C | Page 9 of 44 5 V TIMING SPECIFICATIONS VAA = 4.75 V to 5.25 V,1 VREF = 1.235 V, RSET = 300 Ω. All specifications TMIN to TMAX,2 unless otherwise noted. Table 5. Parameter Conditions Min Typ Max Unit MPU PORT3, 4 SCLOCK Frequency 0 100 kHz SCLOCK High Pulse Width, t1 4.0 µs SCLOCK Low Pulse Width, t2 4.7 µs Hold Time (Start Condition), t3 After this period, the first clock is generated 4.0 µs Setup Time (Start Condition), t4 Relevant for repeated start condition 4.7 µs Data Setup Time, t5 250 ns SDATA, SCLOCK Rise Time, t6 1 µs SDATA, SCLOCK Fall Time, t7 300 ns Setup Time (Stop Condition), t8 4.7 µs ANALOG OUTPUTS3, 5 Analog Output Delay 5 ns DAC Analog Output Skew 0 ns CLOCK CONTROL AND PIXEL PORT3, 4, 6 fCLOCK 27 MHz Clock High Time, t9 8 ns Clock Low Time, t10 8 ns Data Setup Time, t11 3.5 ns Data Hold Time, t12 4 ns Control Setup Time, t11 4 ns Control Hold Time, t12 3 ns Digital Output Access Time, t13 24 ns Digital Output Hold Time, t14 4 ns Pipeline Delay, t15 37 Clock Cycles RESET CONTROL3, 4 RESET Low Time 6 ns INTERNAL CLOCK CONTROL Clock/2 Rise Time, t16 7 ns Clock/2 Fall Time, t17 7 ns OSD TIMING4 OSD Setup Time, t18 6 ns OSD Hold Time, t19 2 ns 1 The max/min specifications are guaranteed over this range. 2 Temperature range TMIN to TMAX: 0°C to 70°C. 3 TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ≤ 10 pF. 4 Guaranteed by characterization. 5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. 6 Pixel port consists of the following: Pixel inputs: P15–P0 Pixel controls: HSYNC, FIELD/VSYNC, BLANK Clock input: CLOCK |
同様の部品番号 - ADV7178_15 |
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同様の説明 - ADV7178_15 |
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