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LF43168QC30 データシート(PDF) 8 Page - LOGIC Devices Incorporated |
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LF43168QC30 データシート(HTML) 8 Page - LOGIC Devices Incorporated |
8 / 16 page DEVICES INCORPORATED LF43168 Dual 8-Tap FIR Filter 8 Video Imaging Products 03/28/2000–LDS.43168-H Figure 5 shows the two possible configurations when the device is programmed as a decimating, even- symmetric coefficient filter. The delay length of the decimation registers will be equal to the decimation factor that the device is programmed for. Since only four coefficients (effectively eight) can be sent to the filter multipli- ers on a clock cycle, it may be neces- sary (depending on the coefficient set) to change the coefficients fed to the multipliers on different CLK cycles for filters with more than eight taps. Note that for the odd-tap filter, the middle coefficient of the coefficient set must be divided by two to get the correct result. Odd-Symmetric Coefficient Filters Figure 6 shows the two possible configurations when the device is programmed for odd-symmetric coefficients. Note that odd-tap, odd- symmetric coefficient filters are not possible. FIGURE 5. DECIMATING, EVEN-SYMMETRIC COEFFICIENT FILTER CONFIGURATIONS COEF 0 COEF 1 COEF 2 COEF 3 B + A AB B + A AB B + A AB B + A AB DATA IN NNN NNN N = Delay Length (Decimation Factor) EVEN-TAP FILTER COEF 0 COEF 1 COEF 2 COEF 3 B + A AB B + A AB B + A AB B + A AB DATA IN NNN NNN N = Delay Length (Decimation Factor) Delay Stage N – 1 Output ODD-TAP FILTER FIGURE 6. ODD-SYMMETRIC COEFFICIENT FILTER CONFIGURATIONS COEF 0 COEF 1 COEF 2 COEF 3 B – A AB B – A AB B – A AB B – A AB DATA IN EVEN-TAP FILTER (NO DECIMATION) COEF 0 COEF 1 COEF 2 COEF 3 B – A AB B – A AB B – A AB B – A AB DATA IN NNN NNN N = Delay Length (Decimation Factor) DECIMATING, EVEN-TAP FILTER |
同様の部品番号 - LF43168QC30 |
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同様の説明 - LF43168QC30 |
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