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74ALVC16836A データシート(PDF) 2 Page - NXP Semiconductors |
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74ALVC16836A データシート(HTML) 2 Page - NXP Semiconductors |
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2 / 12 page  Philips Semiconductors Product specification 74ALVC16836A 20-bit registered driver with inverted register enable (3-State) 2 2000 Mar 14 853–2194 23314 FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Current drive ± 24 mA at 3.0 V • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple V CC and GND pins for minimum noise and ground bounce • Output drive capability 50 Ω transmission lines @ 85°C • Input diodes to accommodate strong drivers DESCRIPTION The 74ALVC16836A is a 20-bit universal bus driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop. When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latch/flip-flop. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 OE NC Y1 Y2 Y3 Y4 Y5 GND VCC GND Y6 Y7 Y8 Y9 Y10 Y11 GND Y12 Y13 Y14 VCC Y15 Y16 GND Y17 CP GND A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND A12 A13 A14 VCC A15 A16 GND A17 SH00197 Y18 Y19 Y20 LE A18 A19 A20 QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay An to Yn; LE to Yn; CP to Yn VCC = 3.3 V, CL = 50 pF 2.3 2.6 2.5 ns fmax Maximum clock frequency VCC = 3.3 V, CL = 50 pF 350 MHz CI Input capacitance 4.0 pF CI/O Input/Output capacitance 8.0 pF C Power dissipation capacitance per buffer V = GND to VCC1 transparent mode Output enabled Output disabled 13 3 pF CPD Power dissipation capacitance per buffer VI = GND to VCC1 Clocked mode Output enabled Output disabled 22 15 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs. |
同様の部品番号 - 74ALVC16836A_15 |
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同様の説明 - 74ALVC16836A_15 |
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