74AVCH2T45_15 datasheet(10/27 Pages) PHILIPS

部品番号	74AVCH2T45

部品情報	Dual-bit, dual-supply voltage level translator/transceiver; 3-state

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74AVCH2T45

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Product data sheet

Rev. 6 — 2 April 2013

10 of 27

NXP Semiconductors

74AVCH2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

11. Dynamic characteristics

[1]

tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.

ten is a calculated value using the formula shown in Section 13.4 “Enable times”

[1]

tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.

ten is a calculated value using the formula shown in Section 13.4 “Enable times”

[1]

CPD is used to determine the dynamic power dissipation (PD in W).

PD =CPD  VCC2  fi  N+ (CL  VCC2  fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(C

L  VCC

2

 f

o) = sum of the outputs.

[2]

fi = 10 MHz; VI =GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL =  .

Table 9.

Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 C [1]

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7

Symbol Parameter

Conditions

VCC(B)

Unit

0.8 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

tpd

propagation delay

A to B

15.8

8.4

8.0

8.7

9.5

ns

B to A

15.8

12.7

12.4

12.2

12.0

11.8

ns

tdis

disable time

DIR to A

12.2

ns

DIR to B

11.7

7.9

7.6

8.2

8.7

10.2

ns

ten

enable time

DIR to A

27.5

20.6

20.0

20.4

20.7

22.0

ns

DIR to B

28.0

20.6

20.2

20.9

21.7

ns

Table 10.

Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 C [1]

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7

Symbol Parameter

Conditions

VCC(A)

Unit

0.8 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

tpd

propagation delay

A to B

15.8

12.7

12.4

12.2

12.0

11.8

ns

B to A

15.8

8.4

8.0

8.7

9.5

ns

tdis

disable time

DIR to A

12.2

4.9

3.8

3.7

2.8

3.4

ns

DIR to B

11.7

9.2

9.0

8.8

8.7

8.6

ns

ten

enable time

DIR to A

27.5

17.6

17.0

16.8

17.4

18.1

ns

DIR to B

28.0

17.6

16.2

15.9

14.8

15.2

ns

Table 11.

Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2]

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

VCC(A) and VCC(B)

Unit

0.8 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

CPD

power dissipation

capacitance

A port: (direction A to B);

B port: (direction B to A)

122

222

pF

A port: (direction B to A);

B port: (direction A to B)

911

11

12

14

17

pF

同様の部品番号 - 74AVCH2T45_15

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同様の説明 - 74AVCH2T45_15

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NXP Semiconductors	74AVC2T45	139Kb / 28P	Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 01 - 3 July 2007
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