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74AVCH8T245 データシート(PDF) 2 Page - NXP Semiconductors |
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74AVCH8T245 データシート(HTML) 2 Page - NXP Semiconductors |
2 / 25 page 74AVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 27 December 2012 2 of 25 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state 260 Mbit/s ( 1.1 V to 2.5 V translation) 210 Mbit/s ( 1.1 V to 1.8 V translation) 150 Mbit/s ( 1.1 V to 1.5 V translation) 100 Mbit/s ( 1.1 V to 1.2 V translation) Suspend mode Bus hold on data inputs Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C 3. Ordering information 4. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVCH8T245PW 40 C to +125 C TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 74AVCH8T245BQ 40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 5.5 0.85 mm SOT815-1 Fig 1. Logic symbol 001aai472 OE DIR VCC(A) VCC(B) 22 2 3 A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 45678910 21 20 19 18 17 16 15 14 |
同様の部品番号 - 74AVCH8T245_15 |
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同様の説明 - 74AVCH8T245_15 |
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