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ADC10D1000QML-SP データシート(PDF) 9 Page - Texas Instruments

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部品番号 ADC10D1000QML-SP
部品情報  ADC10D1000QML Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
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ADC10D1000QML-SP データシート(HTML) 9 Page - Texas Instruments

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50 k:
ADC10D1000QML-SP
www.ti.com
SNAS466F – FEBRUARY 2009 – REVISED APRIL 2013
Table 2-2. Control and Status Pins (continued)
Column
Name
Equivalent Circuit
Description
Power Down I- and Q-channel. Setting either input to
logic-high powers down the respective I- or Q-channel
converter. Setting either input to logic-low brings the
respective I- or Q-channel converter to a fully
operational state after a finite time delay. This pin is
active in both ECM and Non-ECM. In the ECM, either
U3
PDI
this pin or the PDI and PDQ Bit in the Control Register
V3
PDQ
can be used to power-down the I- and Q-channel (Addr:
0h, Bit 11 and Bit 10), respectively.
Test Pattern Mode. With this input at logic-high, the
device continuously outputs a fixed, repetitive test
pattern at the digital outputs. In the ECM, this input is
ignored and the test pattern mode can only be activated
through the Control Register by the TPM Bit (Addr: 0h,
Bit 12).
A4
TPM
Non-Demuxed Mode. Setting this input to logic-high
causes the digital output bus to be in the 1:1 Non-
Demuxed Mode. Setting this input to logic-low causes
the digital output bus to be in the 1:2 Demuxed Mode.
This feature is pin-controlled only and remains active
during ECM and Non-ECM.
A5
NDM
Full-Scale input Range Select. In Non-ECM, when this
input is set to logic-low or logic-high, the full-scale
differential input range for both I- and Q-channel inputs
is set to the lower or higher value, respectively. In the
ECM, this input is ignored and the full-scale range of the
I- and Q-channel inputs is independently determined by
Y3
FSR
the setting of Addr: 3h and Addr: Bh, respectively. Note
that the higher and lower FSR value in Non-ECM does
not precisely correspond to the maximum and minimum
available selection in ECM; in ECM, the selection range
is greater.
DDR Phase Select. This input, when logic-low, selects
the 0-degree Data-to-DCLK phase relationship. When
logic-high, it selects the 90-degree Data-to-DCLK phase
relationship. This pin only has an effect when the chip is
in 1:2 Demuxed Mode, e.g. the NDM pin is set to logic-
low. In ECM, this input is ignored and the DDR phase is
W4
DDRPh
selected through the Control Register by the DPS Bit
(Addr: 0h, Bit 14); the default is 0-degree Data-to-DCLK
phase relationship.
Copyright © 2009–2013, Texas Instruments Incorporated
Device Information
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