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DAC39J84 データシート(PDF) 1 Page - Texas Instruments

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部品番号 DAC39J84
部品情報  DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

DAC39J84 データシート(HTML) 1 Page - Texas Instruments

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DAC39J84
16-bit DAC
16-bit DAC
16-bit DAC
16-bit DAC
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DAC39J84
SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015
DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter
with 12.5 Gbps JESD204B Interface
1 Features
3 Description
The DAC39J84 is a low power, 16-bit, quad-channel,
1
Resolution: 16-Bit
2.8 GSPS digital to analog converter (DAC) with
Maximum Sample Rate: 2.8GSPS
JESD204B interface.
Maximum Input Data Rate: 1.25GSPS
Digital data is input to the device through 1, 2, 4 or 8
JESD204B Interface
configurable serial JESD204B lanes running up to
8 JESD204B Serial Input Lanes
12.5
Gbps
with
on-chip
termination
and
programmable equalization. The interface allows
12.5 Gbps Maximum Bit Rate per Lane
JESD204B Subclass 1 SYSREF based deterministic
Subclass 1 Multi-DAC Synchronization
latency and full synchronization of multiple devices.
On-Chip Very Low Jitter PLL
The device includes features that simplify the design
Selectable 1x -16x Interpolation
of complex transmit architectures. Fully bypassable
Independent Complex Mixers with 48-bit NCO/ or
2x to 16x digital interpolation filters with over 90 dB of
±n×Fs/8
stop-band attenuation simplify the data interface and
reconstruction filters. An on-chip 48-bit Numerically
Wideband Digital Quadrature Modulator
Controlled
Oscillator
(NCO)
and
independent
Correction
complex mixers allow flexible and accurate carrier
Sinx/x Correction Filters
placement.
Fractional Sample Group Delay Correction
A high-performance low jitter PLL simplifies clocking
Multi-Band Mode: Digital Summation of
of the device without significant impact on the
Independent Complex Signals
dynamic range. The digital Quadrature Modulator
Correction (QMC) and Group Delay Correction (QDC)
3/4-Wire Serial Control Bus (SPI)
enable complete IQ compensation for gain, offset,
Integrated Temperature Sensor
phase, and group delay between channels in direct
JTAG Boundary Scan
up-conversion applications. A programmable Power
Pin-Compatible with Quad-Channel
Amplifier (PA) protection mechanism is available to
provide PA protection in cases when the abnormal
DAC37J84/DAC38J84 Family
power behavior of the input data is detected.
Power Dissipation: 1.8W at 2.8GSPS
Package: 10 mm x 10 mm, 144-Ball Flip-Chip
Device Information(1)
BGA
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DAC39J84
FCBGA (144)
10.00 mm x 10.00 mm
2 Applications
(1) For all available packages, see the orderable addendum at
Cellular Base Stations
the end of the datasheet.
Diversity Transmit
Wideband Communications
Direct Digital Synthesis (DDS) instruments
Defense/Military
Millimeter/Microwave Backhaul
Automated Test Equipment
Cable Infrastructure
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


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