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DAC5675-EP データシート(PDF) 7 Page - Texas Instruments |
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DAC5675-EP データシート(HTML) 7 Page - Texas Instruments |
7 / 28 page www.ti.com Digital Specifications DAC5675-EP SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006 over operating free-air temperature range, typical values at 25 °C, AV DD = 3.3 V, DVDD = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVDS Interface: Nodes D[13:0]A, D[13:0]B Positive-going differential input VITH+ 100 mV voltage threshold See LVDS Min/Max Threshold Voltages table Negative-going differential input VITH– –100 mV voltage threshold ZT Internal termination impedance 90 110 132 Ω CI Input capacitance 2 pF CMOS Interface (SLEEP) VIH High-level input voltage 2 3.3 V VIL Low-level input voltage 0 0.8 V IIH High-level input current –100 100 µA IIL Low-level input current –10 10 µA Input capacitance 2 pF Clock Interface (CLK, CLKC) |CLK-CLKC| Clock differential input voltage 0.4 0.8 VPP tw(H) Clock pulse width high 1.25 ns tw(L) Clock pulse width low 1.25 ns Clock duty cycle 40% 60% VCM Common-mode voltage range 2 ± 20% V Input resistance Node CLK, CLKC 670 Ω Input capacitance Node CLK, CLKC 2 pF Input resistance Differential 1.3 k Ω Input capacitance Differential 1 pF Timing tSU Input setup time 1.5 ns tH Input hold time 0.25 ns tLPH Input latch pulse high time 2 ns tDD Digital delay time DLL disabled, DLLOFF = 1 3 clk 7 Submit Documentation Feedback |
同様の部品番号 - DAC5675-EP_15 |
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同様の説明 - DAC5675-EP_15 |
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