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GS2961A データシート(PDF) 5 Page - Gennum Corporation |
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GS2961A データシート(HTML) 5 Page - Gennum Corporation |
5 / 104 page GS2961A 3Gb/s, HD, SD SDI Integrated Receiver Data Sheet 54385 - 2 September 2012 5 of 104 List of Figures Figure 3-1: Digital Input Pin with Schmitt Trigger............................................................................... 22 Figure 3-2: Bidirectional Digital Input/Output Pin..............................................................................22 Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength ........ 23 Figure 3-4: XTAL1/XTAL2/XTAL-OUT ................................................................................................... 23 Figure 3-5: VBG .............................................................................................................................................. 24 Figure 3-6: LB_CONT .................................................................................................................................... 24 Figure 3-7: Loop Filter .................................................................................................................................. 24 Figure 3-8: SDO/SDO .................................................................................................................................... 25 Figure 3-9: Equalizer Input Equivalent Circuit .................................................................................... 25 Figure 4-1: Level A Mapping ...................................................................................................................... 27 Figure 4-2: Level B Mapping ...................................................................................................................... 27 Figure 4-3: GS2961A Integrated EQ Block Diagram .......................................................................... 28 Figure 4-4: 27MHz Clock Sources ............................................................................................................ 31 Figure 4-5: PCLK to Data and Control Signal Output Timing - SDR Mode 1 .............................. 34 Figure 4-6: PCLK to Data and Control Signal Output Timing - SDR Mode 2 .............................. 35 Figure 4-7: PCLK to Data and Control Signal Output Timing - DDR Mode ................................. 36 Figure 4-8: DDR Video Interface - 3G Level A ..................................................................................... 39 Figure 4-9: DDR Video Interface - 3G Level B ...................................................................................... 40 Figure 4-10: Delay Adjustment Ranges .................................................................................................. 41 Figure 4-11: Switch Line Locking on a Non-Standard Switch Line ............................................... 42 Figure 4-12: H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode .................................... 46 Figure 4-13: H:V:F Output Timing - 3G Level A and HDTV 10-bit Mode 3G Level B 20-bit Mode, each 10-bit stream ......................................................................................... 47 Figure 4-14: H:V:F Output Timing - 3G Level B 10-bit Mode .......................................................... 47 Figure 4-15: H:V:F Output Timing - HD 20-bit Output Mode ......................................................... 47 Figure 4-16: H:V:F Output Timing - HD 10-bit Output Mode ......................................................... 47 Figure 4-17: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 47 Figure 4-18: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 47 Figure 4-19: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 49 Figure 4-20: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 50 Figure 4-21: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .................... 51 Figure 4-22: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 51 Figure 4-23: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 52 Figure 4-24: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 53 Figure 4-25: H:V:DE Output Timing 1920 x 1080p @ 59.94/60 (Format 16) .............................. 53 Figure 4-26: H:V:DE Output Timing 1920 x 1080p @ 50 (Format 31) .......................................... 54 Figure 4-27: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 54 Figure 4-28: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 55 Figure 4-29: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 55 Figure 4-30: 2K Feature Enhancement ................................................................................................... 59 Figure 4-31: Y/1ANC and C/2ANC Signal Timing .............................................................................. 66 Figure 4-32: Ancillary Data Extraction - Step A .................................................................................. 73 Figure 4-33: Ancillary Data Extraction - Step B ................................................................................... 74 Figure 4-34: Ancillary Data Extraction - Step C .................................................................................. 74 Figure 4-35: Ancillary Data Extraction - Step D .................................................................................. 75 Figure 4-36: GSPI Application Interface Connection ........................................................................ 77 Figure 4-37: Command Word Format ..................................................................................................... 78 Figure 4-38: Data Word Format ................................................................................................................ 78 Figure 4-39: Write Mode .............................................................................................................................. 79 Figure 4-40: Read Mode ............................................................................................................................... 79 Figure 4-41: GSPI Time Delay .................................................................................................................... 79 Figure 4-42: In-Circuit JTAG ...................................................................................................................... 95 |
同様の部品番号 - GS2961A |
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同様の説明 - GS2961A |
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