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TDA21231 データシート(PDF) 10 Page - Infineon Technologies AG |
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TDA21231 データシート(HTML) 10 Page - Infineon Technologies AG |
10 / 19 page TDA21231 Data Sheet 9 Referring to the block diagram page 4, VCC is internally connected to the UVLO circuit. It will force shut-down for insufficient VCC voltage. PVCC supplies the floating high-side drive – consisting of an active boot circuit - and the low side drive circuit. During undervoltage both GH and GL are driven low actively; further passive pull- down (10 k ) is placed across gate-source of both FETs. An additional UVLO circuitry, sensing the BOOT voltage level, is implemented to enable a recharge of the boot capacitor when its voltage is too low for a complete turn-on of the HS-MOSFET. 5.2 Inputs to the Internal Control Circuits The PWM is the control input to the IC from an external PWM controller and is compatible with 3.3 V. The PWM input has tri-state functionality. When the voltage remains in the specified PWM-shutdown-window for at least the PWM-shutdown-holdoff time t_tsshd, the operation will be suspended by keeping both MOSFET gate outputs low. Once left open, the pin is held internally at a level of VPWM_O = 1.6 V level. Table 12 PWM Pin Functionality PWM logic level Driver output Low GL= High, GH = Low High GL = Low, GH = High Open (left floating, or High impedance) GL = Low, GH = Low The PWM threshold voltages VPMW_O, VPWM_H, VPWM_L do not vary over the wide range of VCIN supply voltages (4.5 V to 8 V). The EN is an active high signal. When EN is being pulled low, the power stage will be disabled. Figure 4 Enable (EN) signal logic levels VCC “H” “L” VEN_L VEN_H EN Logic Level Shutdown Enable |
同様の部品番号 - TDA21231_15 |
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同様の説明 - TDA21231_15 |
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