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ISL29038IROZ-EVALZ データシート(PDF) 6 Page - Intersil Corporation

部品番号 ISL29038IROZ-EVALZ
部品情報  Low Power Ambient Light and Proximity Sensor with Enhanced Infrared Rejection
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メーカー  INTERSIL [Intersil Corporation]
ホームページ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL29038IROZ-EVALZ データシート(HTML) 6 Page - Intersil Corporation

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ISL29038
6
FN7851.1
January 23, 2015
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ISL29038 Configuration and
Control
I2C Interface
ISL29038 configuration and control is performed using the I2C
or SMBus. The ISL29038’s I2C interface slave address is
internally hard wired as 8’b1000100x, where x denotes the R/W
bit.
Every I2C transaction begins with the master asserting a start
condition (SDA falling while SCL remains high). The first
transmitted byte is initiated by the master and includes 7
address bits and a R/W bit. The slave is responsible for pulling
SDA low during the ACK time after every transmitted byte.
Figure 5 shows a sample one-byte read. The I2C bus master
always drives the SCL (clock) line, while either the master or the
slave can drive the SDA (data) line.
Each I2C transaction ends with the master asserting a stop
condition (SDA rising while SCL remains high). For more
information about the I2C standard, consult the PhilipsI2C
specification documents.
Timing specifications are included in “I2C Electrical
Specifications” on page 4. The timing parameters are defined in
Figure 4.
The I2C interface on the ISL29038 supports single and multiple
byte read and write transfers using the random-read/write
protocol. The ISL29038 does not support I2C ‘Repeat Start’
protocol.
NOTE: That in most system implementations, the ISL29038 is connected
to a single I2C master with one or more slave devices, consequently,
absence of ‘Repeat Start’ function does not adversely affect I2C bus
system performance.
FIGURE 5. I2C DRIVER TIMING DIAGRAM FOR MASTER AND SLAVE CONNECTED TO COMMON BUS
START
W A
A
A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A
A6 A5 A4 A3 A2 A1 A0 W A
A
A
A D7 D6 D5 D4 D3D2 D1D0
13
5
7
13
57
1 2 3
4 5
6
9
2
4
6
STOP START
SDA DRIVEN BY MASTER
DEVICE ADDRESS
SDA DRIVEN BY ISL29038
DATA BYTE0
REGISTER ADDRESS
SLAVE
DEVICE ADDRESS
I2C DATA
SDA DRIVEN BY MASTER
SDA DRIVEN BY MASTER
24
68 9
2
468 9
7
8
1
3
5
7 8
9
I2C SDA
I2C SDA
I2C CLK
MASTER
(ISL29038)


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