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93C56A データシート(PDF) 5 Page - Microchip Technology |
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93C56A データシート(HTML) 5 Page - Microchip Technology |
5 / 12 page © 1998 Microchip Technology Inc. Preliminary DS21206B-page 5 93C56A/B 3.4 ERASE The ERASE instruction forces all data bits of the spec- ified address to the logical “1” state. This cycle begins on the rising clock edge of the last address bit. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical “0” indicates that program- ming is still in progress. DO at logical “1” indicates that the register at the specified address has been erased and the device is ready for another instruction. 3.5 Erase All (ERAL) The ERAL instruction will erase the entire memory array to the logical “1” state. The ERAL cycle is identical to the ERASE cycle, except for the different opcode. The ERAL cycle is completely self-timed and com- mences at the rising clock edge of the last address bit. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle. The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire ERAL cycle is com- plete. FIGURE 3-2: ERASE TIMING FIGURE 3-3: ERAL TIMING CS CLK DI DO TCSL CHECK STATUS 1 1 1AN AN-1 AN-2 ••• A0 TSV TCZ BUSY READY HIGH-Z TWC HIGH-Z CS CLK DI DO TCSL CHECK STATUS 10 0 1 0 X ••• X TSV TCZ BUSY READY HIGH-Z TEC HIGH-Z |
同様の部品番号 - 93C56A |
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同様の説明 - 93C56A |
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