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93AA66-SM データシート(PDF) 5 Page - Microchip Technology |
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93AA66-SM データシート(HTML) 5 Page - Microchip Technology |
5 / 12 page © 1996 Microchip Technology Inc. DS20067G-page 5 93AA46/56/66 2.8 Erase All (ERAL) The ERAL instruction will erase the entire memory array to the logical “1” state. The ERAL cycle is identical to the ERASE cycle except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The ERAL instruction is guaranteed at 5V ± 10%. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. The ERAL cycle takes (8 ms typical). 2.9 Write All (WRAL) The WRAL instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The WRAL command does include an auto- matic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The WRAL instruc- tion is guaranteed at 5V ± 10%. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). The WRAL cycle takes 16 ms typical. FIGURE 2-1: SYNCHRONOUS DATA TIMING FIGURE 2-2: READ TIMING CLK STATUS VALID VIH VIL CS TCSS TDIS TDIH TSV TCSH TCKH TCKL TPD TCZ TCZ TPD VIH VIL DI VIH VIL DO (READ) VOH VOL DO (PROGRAM) VOH VOL Tri-State is a registered trademark of National Semiconductor Incorporated. CLK CS TCSL • A • • • A0 0 1 1 DI DO Dx • • • D0 0 Dx* • • • D0 Dx* TRI-STATE™ n D0 • • • TRI-STATE® |
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同様の説明 - 93AA66-SM |
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