LM2647

SNVS210F – JUNE 2003 – REVISED APRIL 2013

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PIN DESCRIPTION (continued)

Pin 10, FPWM: Logic input for selecting either the Forced PWM (FPWM) Mode or Pulse-skip Mode (SKIP) for both channels (together).

When the pin is driven high, the IC operates in the FPWM mode, and when pulled low or left floating, the SKIP mode is enabled. In FPWM

mode, the lower FET of a given channel is always ON whenever the upper FET is OFF (except for a narrow shoot-through protection

deadband). This leads to continuous conduction mode of operation, which has a fixed frequency and (almost) fixed duty cycle down to very

light loads. But this does reduce efficiency at light loads. The alternative is the SKIP mode, where the lower FET remains ON only until the

voltage on the Switch pin (see Pin 27 or Pin 16) is more negative than 2.2mV (typical). So for example, for a 21m

Ω FET, this translates to a

current threshold of 2.2mV/21m

Ω = 0.1A. Therefore, if the (instantaneous) inductor current falls below this value, the lower FET will turn

OFF every cycle at this point (when operated in SKIP mode). This threshold is set by the zero-cross Comparator in the Figure 4. Note that if

Characteristics), there will be no observable difference between FPWM and SKIP mode settings (in steady-state). SKIP mode, when it

actually occurs, is clearly a discontinuous mode of operation. However, note that in conventional discontinuous mode, the duty cycle keeps

falling (towards zero) as the load decreases. But the LM2647 does not allow the duty cycle to fall by more than 15% of its original value (at

the CCM-DCM boundary). This forces pulse-skipping, and the average frequency is effectively decreased as the load decreases. This

mode of operation improves efficiency at light loads, but the frequency is effectively no longer a constant. Note that a minimum pre-load of

0.1mA should be maintained on the output of each channel to ensure regulation in SKIP mode. The resistive divider from output to ground

used to set the output voltage could be designed to serve as part or all of this required pre-load.

Pin 11, SS2: Soft-start pin for Channel 2. See Pin 4.

Pin 12, COMP2: Soft-start pin for Channel 2. See Pin 3.

Pin 13, FB2: Feedback pin for Channel 2. See Pin 2.

Pin 14, SENSE2: Output voltage sense pin for Channel 2. See Pin 1.

Pin 15, ILIM2: Channel 2 Current Limit pin. When the bottom FET is ON, a 62µA (typical) current flows out of this pin into an external

current limit setting resistor connected to the Drain of the lower FET. This is a current source, therefore the drop across this resistor serves

to push the voltage on this pin to a more positive value. However, the Drain of the lower FET which is connected to the other side of the

same resistor is trying to go more negative as the load current increases. At some value of instantaneous current, the voltage on this pin

will transit from positive to negative. The point where it is zero is the current limiting condition and is detected by the Current Limit

Comparator in the Figure 4. When current limit condition has been detected, the next ON-pulse of the upper FET will be omitted. The lower

FET will again be monitored to determine if the current has fallen below the threshold. If it has, the next ON-pulse will be permitted. If not,

the upper FET will be turned OFF and will stay so for several cycles if necessary, until the current returns to normal. Eventually, if the

overcurrent condition persists, and the upper FET has not been turned ON, the output will clearly start to fall. Ultimately the output will fall

below the under-voltage threshold, and a fault condition will be asserted by the IC.

Pin 16, SW2: The Switching node of the buck regulator of Channel 2. Also serves as the lower rail of the floating driver of the upper FET.

Pin 17, HDRV2: Gate drive pin for the upper FET of Channel 2 (High-side drive). The top gate driver is interlocked with the bottom gate

driver to prevent shoot-through/cross-conduction.

Pin 18, BOOT2: Bootstrap pin for Channel 2. This is the upper supply rail for the floating driver of the upper FET. It is bootstrapped by

means of a ceramic capacitor connected to the channel Switching node. This capacitor is charged up by the IC to a value of about 5V as

derived from the V5 pin (Pin 21).

Pin 19, PGND2: Power Ground pin of Channel 2. This is the return path for the bottom FET gate drive. Both the PGND's are to be

connected on the PCB to the system ground and also to the Signal ground (Pin 7) in accordance with the recommended LAYOUT

GUIDELINES.

Pin 20, LDRV2: Gate drive pin for the Channel 2 bottom FET (Low-side drive). The bottom gate driver is interlocked with the top gate driver

to prevent shoot-through/cross-conduction. It is always latched high when a fault condition is asserted by the IC.

Pin 21, V5: Upper rail of the lower FET drivers of both channels. Also used to charge up the bootstrap capacitors of the upper FET drivers.

This is connected to an external 5V supply. The 5V rail may be the same as the rail used to provide power to the VDD pin (Pin 5), but the

VDD pin will then require to be well-decoupled so that it does not interact with the V5 pin. A low-pass RC filter consisting of a ceramic 0.1µF

capacitor (preferably 0.22µF) and a 10

Ω resistor will suffice as shown in the Typical Applications circuit.

Pin 22, VIN: The input to both the Buck regulator power stages. It also is used by the internal ramp generator to implement the line

feedforward feature. The VIN pin is also used with the SENSE pin voltage to predict the CCM (continuous conduction mode) duty cycle and

to thereby set the minimum allowed DCM duty cycle to 85% of the CCM value (in SKIP mode, see Pin 10). This is a high input impedance

pin, drawing only about 100µA (typical) from the input rail.

Pin 23, LDRV1: LDRV pin of Channel 1. See Pin 20.

Pin 24, PGND1: PGND pin for Channel 1.See Pin 19.

Pin 25, BOOT1: Boot pin of Channel 1. See Pin 18.

Pin 26, HDRV1: HDRV pin of Channel 1. See Pin 17.

Pin 27, SW1: SW pin of Channel 1. See Pin 16.

Pin 28, ILIM1: Channel 2 Current Limit pin. See Pin 15.

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