データシートサーチシステム |
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LM3489 データシート(PDF) 2 Page - Texas Instruments |
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LM3489 データシート(HTML) 2 Page - Texas Instruments |
2 / 25 page ISENSE GND PGND VIN PGATE ADJ FB EN 1 2 3 4 5 6 7 8 LM3489 LM3489-Q1 SNVS443B – MAY 2006 – REVISED FEBRUARY 2013 www.ti.com CONNECTION DIAGRAM Figure 1. Top View 8-Lead Plastic VSSOP-8 Package Number (DGK) PIN DESCRIPTIONS Pin Name Description No. 1 ISENSE The current sense input pin. This pin should be connected to the PFET drain terminal directly or through a series resistor up to 600 ohm for 28V>Vin>35V. 2 GND Signal ground. 3 EN Enable pin. Connect EN pin to ground to shutdown the part or float to enable operation (Internally pulled high). This pin can also be used to perform UVLO function. 4 FB The feedback input. Connect the FB to a resistor voltage divider between the output and GND for an adjustable output voltage. 5 ADJ Current limit threshold adjustment. Connected to an internal 5.5µA current source. A resistor is connected between this pin and VIN. The voltage across this resistor is compared with the ISENSE pin voltage to determine if an over-current condition has occurred. 6 PGND Power ground. 7 PGATE Gate Drive output for the external PFET. PGATE swings between VIN and VIN-5V. 8 VIN Power supply input pin. 2 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 |
同様の部品番号 - LM3489_15 |
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同様の説明 - LM3489_15 |
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