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TEA1795T データシート(PDF) 4 Page - NXP Semiconductors |
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4 / 14 page TEA1795T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 — 4 November 2010 4 of 14 NXP Semiconductors TEA1795T GreenChip synchronous rectifier controller 7.2 Start-up and UnderVoltage LockOut (UVLO) The IC leaves the UVLO state and activates the synchronous rectifier circuitry when the voltage on the VCC pin is above Vstartup (8.5 V typical). When the voltage drops below 8.0 V (typical), the UVLO state is reentered and the SR MOSFET gate driver outputs are actively kept low. 7.3 Supply management All (internal) reference voltages are derived from a temperature compensated, on-chip band gap circuit. 7.4 Synchronous rectification (DSA, SSA, DSB and SSB pins) The voltages present between the drain and source terminals of the SR MOSFETs are used to derive the timing for the gate drive signal. The IC senses the voltage difference between the drain sense (pins DSA and DSB) and the source sense (pins SSA and SSB) connections. When this voltage difference is lower than Vact(drv) (−220 mV typical), the corresponding gate driver output voltage is driven high and the external SR MOSFET is switched on. When the external SR MOSFET is switched on, the input signals on the drain sense pins and source sense pins are ignored during the minimum synchronous rectification active time (tact(sr)(min), 520 ns typical). This minimizes false switch-off due to the sensing of high frequency ringing signals at the start of the conduction phase. Once this minimum synchronous rectification active time has ended, the IC monitors the difference between the drain sense inputs and the source sense inputs. When the difference is higher than Vreg(drv) (−25 mV typical), the gate driver output voltage is regulated to maintain this −25 mV difference between the drain sense pins and the source sense pins. As a result, the SR MOSFET can be switched off quickly when the current through the external SR MOSFET reaches zero. Fig 3. TEA1795T: typical configuration 001aal797 DSA GDA SSA DSB VCC GDB SSB GND Qprim1 CHB RDRNSENSE1 Qprim2 Qsec1 PRIMARY SIDE CONTROLLER TEA1795T Vin Vout TR IC1 RDRNSENSE2 Qsec2 Cout |
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