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LM26001B データシート(PDF) 9 Page - Texas Instruments |
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LM26001B データシート(HTML) 9 Page - Texas Instruments |
9 / 27 page sleep wake 0.6V 2 PA + - 0.9V V clamp + - + - SS logic + - TSD VDD_low ss end blanking qn qn fpwm Sync and bootstrap control fpwm LG LG 5 PA VDD_low EN FB SW SW FPWM COMP PGOOD SS GND SYNC BOOT VIN VBIAS VDD VIN SD + - + - + - Clock / Sync BG BG + I Sense PWM Comp BG IREF TSD FPWM / Sleep Peak Current Control Sleep Reset EA PG 0.92BG + - Corrective Ramp PWM Control Logic + - + - Sleep Set LDO UVLO on Switchover control VREG sleep EP frequency foldback FREQ soft start on SD ff ff LM26001B www.ti.com SNVS491B – MAY 2007 – REVISED APRIL 2013 Block Diagram Operation Description GENERAL The LM26001B is a current mode PWM buck regulator. At the beginning of each clock cycle, the internal high- side switch turns on, allowing current to ramp up in the inductor. The inductor current is internally monitored during each switching cycle. A control signal derived from the inductor current is compared to the voltage control signal at the COMP pin, derived from the feedback voltage. When the inductor current reaches the threshold, the high-side switch is turned off and inductor current ramps down. While the switch is off, inductor current is supplied through the catch diode. This cycle repeats at the next clock cycle. In this way, duty cycle and output voltage are controlled by regulating inductor current. Current mode control provides superior line and load regulation. Other benefits include cycle by cycle current limiting and a simplified compensation scheme. Typical PWM waveforms are shown in Figure 15. Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LM26001B |
同様の部品番号 - LM26001B_15 |
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同様の説明 - LM26001B_15 |
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