TCP−3047N

http://onsemi.com

4

ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE

The following assembly considerations should be observed:

Cleanliness

These chips should be handled in a clean environment

.

Electro-static Sensitivity

ON Semiconductor’s PTICs are ESD Class 1A sensitive.

The proper ESD handling procedures should be used.

Mounting

The WLCSP PTIC is fabricated for Flip Chip solder

mounting. Connectivity to the RF and Bias terminations on

the PTIC die is established through copper pillar posts

(53

mm nominal height) topped with lead-free SAC351

solder caps (28

mm nominal height). The PTIC die is

RoHS-compliant and compatible with lead-free soldering

profile.

Post-reflow Cleaning

Use of ultrasonic cleaning is not recommended for

pillared devices as it may lead to premature fatigue failure

of the pillars.

Molding

The PTIC die is compatible for over-molding or

under-fill.

Figure 5. Reflow Profile

ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES

When configuring the PTIC in your specific circuit

design, at least one of the RF terminals must be connected

to DC ground. If minimum transition times are required, DC

ground on both RF terminals is recommended. To minimize

losses, the PTIC should be oriented such that RF2 is at the

lower RF impedance of the two RF nodes. A shunt PTIC, for

example, should have RF2 connected to RF ground.

Figure 6. PTIC Orientation Functional Block

Diagram

Bias

RF

ANT

RF1

(PTIC Pad)

RF2

(PTIC Pad)