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LC717A10AR データシート(PDF) 6 Page - ON Semiconductor |
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LC717A10AR データシート(HTML) 6 Page - ON Semiconductor |
6 / 11 page LC717A10AR No.A2161-6/11 I 2C Compatible Bus Slave Address Selection of two kinds of addresses is possible through the SA0 and SA1 terminals. SA1 input SA0 input 7bit slave address Binary notation 8bit slave address 00101100b (Write) 0x2C Low Low 0x16 00101101b (Read) 0x2D 00101110b (Write) 0x2E Low High 0x17 00101111b (Read) 0x2F 00110000b (Write) 0x30 High Low 0x18 00110001b (Read) 0x31 00110010b (Write) 0x32 High High 0x19 00110011b (Read) 0x33 SPI Data Timing (SPI Mode 0 / Mode 3) fig.5 SPI Communication Formats (Example of Mode 0) • Write format (data can be written into sequentially incremented addresses with preserving nCS = L) nCS SCK SI SO 7 6543 2 10 Hi-Z Register Address(N) Data written to Register Address(N) Data written to Register Address(N+1) Write=L 7 6543 2 10 76 543 2 10 fig.6 • Read format (data can be read from sequentially incremented addresses with preserving nCS = L) Register Address(N) Data read from Register Address(N) Data read from Register Address(N+1) 7 Read=H 76543 2 10 Hi-Z nCS SCK SI SO 76 5 4 3 2 10 76543 2 10 fig.7 nCS SCK SI SO tSU;SI VALID Hi-Z tr tHD;SI tSU;SCK tSU;NCS tHIGH tLOW tf tCPH tHD;NCS tHD;SCK tCLZ tHD;SO tCHZ VALID tV |
同様の部品番号 - LC717A10AR |
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同様の説明 - LC717A10AR |
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