SM5170AV

NIPPON PRECISION CIRCUITS—8

Input data format example

Reference frequency divider = 144, LD normal operation:

Standby Mode

The SM5170AV enters standby mode when OPR

goes LOW. In this mode, the states and functions

shown in the table occur.

In standby mode, some current flows into VDD1.

fully reduce current consumption and reduce power

supplies are reduced to 0 V, the latch contents will be

0 V.

goes HIGH.

Phase Comparator Timing Diagram

The DO output circuit polarity is configured for con-

nection to an external passive filter.

The signals compared are FV and FR, which are the

internal FIN input frequency divider output signal

and reference frequency divider output signal,

respectively.

Figure 6. Reference counter data and LD output setting example

12

345

678

9

10

11

12

13

14

15

16

17

MSB

18

19

20

21

22

23

LSB

22

222

222

22

222

2

15

14

13

12

11

10

9

8

7

6

5

4

3

2

22

10

00

000

000

10

010

000

0

00

100

0

24

1

Reference Counter (16bit : 5 to 65535)

Control bits

Not used (set to 000)

LDpin Set bit

Test bits (set to 00)

Block

State

DO and DB

Floating (high impedance)

L D

L O W -level output

Phase comparator

Reset

Input FIN

F eedback resistor is cutoff (HIGH level)

Input XIN

F eedback resistor is cutoff (HIGH level)

N counter

Reset

R counter

Reset

Latch data

Figure 7. Phase comparator timing

FR

FV

DO

LD