LC709006A

No.8265-5/14

Switching I/O Characteristics at Ta=-40 to +85

°C, VDD=VDDP0=VDDP1=VDDP2, VSS=VSSP0=VSSP1=VSSP2, VSS=0V

Parameter

Symbol

Pin/Remarks

Conditions

Specification

Unit

VDD[V]

min

typ

max

Clock setup time

TsCLK

CS, CLK

•Specified with

respect to falling

edge of CS.

•See Fig. 9.

2.0 to 6.0

100

ns

Chip select low level setup

time

TslCS

CS, CLK

•Specified with

respect to falling

edge of CS.

•See Fig. 9.

2.0 to 6.0

100

Chip select low level hold

time

ThlCS

CS, CLK

•Specified with

respect to falling

edge of CS.

•See Fig. 9.

2.0 to 6.0

100

Clock hold time

ThCLK

CS, CLK

•Specified with

respect to falling

edge of CS.

•See Fig. 9.

2.0 to 6.0

200

Clock low level pulse width

TwlCLK

CLK

•See Fig. 9.

4.5 to 6.0

250

2.7 to 6.0

500

2.0 to 6.0

1000

Clock high level pulse

width

TwhCLK

CLK

•See Fig. 9.

4.5 to 6.0

250

2.7 to 6.0

500

2.0 to 6.0

1000

Chip select high level

setup time

TshCS

CS, RES

•See Fig. 9.

2.0 to 6.0

200

Chip select high level hold

time

ThhCS

CS, RES

•See Fig. 9.

2.0 to 6.0

100

Chip select low level pulse

width

TwlCS

CS, RES

•See Fig. 9.

2.0 to 6.0

200

Reset low level pulse width

TwlRES

CS, RES

•See Fig. 9.

2.0 to 6.0

150

Data setup time

TsDIN

DIN

•Specified with

respect to falling

edge of CLK.

•See Fig. 9.

4.5 to 6.0

30

2.0 to 6.0

50

Data hold time

ThDIN

DIN

•Specified with

respect to falling

edge of CLK.

•See Fig. 9.

4.5 to 6.0

50

2.7 to 6.0

150

2.0 to 6.0

300

Serial data output delay

time

(Note 4)

TdD0UT

DOUT

•Specified with

respect to falling

edge of CLK.

•See Fig. 9.

4.5 to 6.0

200

2.7 to 6.0

400

2.0 to 6.0

800

Port data output delay time

TdPOUT

Port 0 to 2

•Specified with

respect to rising

edge of CS.

•See Fig. 9.

4.5 to 6.0

200

2.7 to 6.0

400

2.0 to 6.0

800

Port data input setup time

TsPIN

Port 0 to 2

•Specified with

respect to rising

edge of CLK.

•See Fig. 9.

4.5 to 6.0

30

2.0 to 6.0

50

Port data input hold time

ThPIN

Port 0 to 2

•Specified with

respect to rising

edge of CLK.

•See Fig. 9.

4.5 to 6.0

50

2.7 to 6.0

150

2.0 to 6.0

300

Note 4: The input data of P00 will be out from DOUT terminal at the first negative edge of CLK signal. Because of this,

Serial data output delay time of the first clock will be the time measured from the negative edge of the CLK or

the time at the input data (P00) is settled.