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SM5841H データシート(PDF) 11 Page - Nippon Precision Circuits Inc |
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SM5841H データシート(HTML) 11 Page - Nippon Precision Circuits Inc |
11 / 20 page SM5841H NIPPON PRECISION CIRCUITS—11 FUNCTIONAL DESCRIPTION The basic arithmetic block is shown in figure 1, and the function of each block is described in the follow- ing sections. 8-times Oversampling (Interpolation) The interpolation arithmetic block is comprised of 3 cascaded, 2-times FIR interpolation filters, as shown in figure 1. The input signal is sampled at rate fs, and then 8- times oversampling data is output. Sampling noise in the 0.5465fs to 7.4535fs stopband is removed by the interpolation filter. Digital Deemphasis (DSF1, DSF2) The digital deemphasis filter has the same construc- tion as analog filters. It is implemented as an IIR fil- ter to faithfully reproduce the gain and phase characteristics of standard analog deemphasis filters. The filter coefficients for fs = 32.0/44.1/48.0 kHz sampling frequency are selected by DSF1 and DSF2 when the sampling frequency is specified, as shown in the following table. Figure 1. Arithmetic block diagram Input fs 13th - order 2 × interpolator 2fs 4fs 69th - order 2 × interpolator 8fs fs fs fs 9th - order 2 × interpolator Attenuator Deemphasis IIR filter 1st FIR 3rd FIR 2nd FIR Output DSF1 DSF2 Deemphasis Sampling frequency LOW LOW On 44.1 kHz LOW HIGH On 48.0 kHz HIGH LOW Off – HIGH HIGH On 32.0 kHz |
同様の部品番号 - SM5841H |
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同様の説明 - SM5841H |
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