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ACE25Q400G データシート(PDF) 3 Page - ACE Technology Co., LTD. |
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ACE25Q400G データシート(HTML) 3 Page - ACE Technology Co., LTD. |
3 / 46 page ACE25Q400G 4M BIT SPI NOR FLASH Memory Series VER 1.2 3 Signal Description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or VOL, see Section 8.6, DC Electrical Characteristics on page 40). These signals are Signal Names Table 1 Pin No Pin Name I/O Description 1 /CS I Chip Select 2 SO (IO1) I/O Serial Output for single bit data Instructions. IO1 for Dual or Quad Instructions. 3 /WP (IO2) I/O Write Protect in single bit or Dual data Instructions. IO2 in Quad mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad Instructions. 4 VSS Ground 5 SI (IO0) I/O Serial Input for single bit data Instructions. IO0 for Dual or Quad Instructions. 6 SCLK I Serial Clock 7 /HOLD# (IO3) I/O Hold (pause) serial transfer in single bit or Dual data Instructions. IO3 in Quad-I/O mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad Instructions. 8 VCC Core and/ O Power Supply Ordering information ACE25Q400G UA8 + X H U: Tube T: Tape and Reel Pb - free UA8: USON8 3*2 (0.75-0.50mm) Halogen-free 400:4M bit |
同様の部品番号 - ACE25Q400G |
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同様の説明 - ACE25Q400G |
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