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TMP275 データシート(PDF) 11 Page - Texas Instruments |
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TMP275 データシート(HTML) 11 Page - Texas Instruments |
11 / 33 page SCL SDA t (LOW) t R t F t (HDSTA) t (HDSTA) t (HDDAT) t (BUF) t (SUDAT) t (HIGH) t (SUSTA) t (SUSTO) P S S P TMP275 www.ti.com SBOS363E – JUNE 2006 – REVISED NOVEMBER 2015 7.3.4.5 High-speed Mode For the Two-Wire bus to operate at frequencies above 400 kHz, the master device must issue an Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP1275 device will not acknowledge this byte, but will switch their input filters on SDA and SCL and their output filters on SDA to operate in Hs-mode, allowing transfers at up to 2.38 MHz. After the Hs-mode master code has been issued, the master will transmit a Two-Wire slave address to initiate a data transfer operation. The bus will continue to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP275 switches the input and output filter back to fast-mode operation. 7.3.4.6 Time-out Function The TMP275 resets the serial interface if either SCL or SDA is held LOW for 54 ms (typical) between a START and STOP condition. The TMP275 releases the bus if it is pulled LOW and waits for a START condition. To avoid activating the time-out function, it is necessary to maintain a communication speed of at least 1 kHz for SCL operating frequency. 7.3.5 Timing Diagrams The TMP275 is Two-Wire, SMBUs, and I2C interface-compatible. Figure 7 to Figure 10 describe the various operations on the TMP275. Bus definitions are given below. Parameters for Figure 7 are defined in Timing Requirements. Bus Idle: Both SDA and SCL lines remain HIGH. Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START condition. Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data. Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a Not-Acknowledge on the last byte that has been transmitted by the slave. 7.3.6 Two-Wire Timing Diagrams Figure 7. Two-Wire Timing Diagram Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TMP275 |
同様の部品番号 - TMP275_15 |
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同様の説明 - TMP275_15 |
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