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TPS28226DG4 データシート(PDF) 3 Page - Texas Instruments |
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TPS28226DG4 データシート(HTML) 3 Page - Texas Instruments |
3 / 39 page 5 3 7 6 8 1 2 BOOT PWM VDD EN/PG GND PHASE 4 Exposed Thermal Die Pad LGATE UGATE 1 2 3 4 8 7 6 5 UGATE BOOT PWM GND PHASE EN/PG VDD LGATE TPS28226 www.ti.com SLUS791A – JULY 2007 – REVISED SEPTEMBER 2015 5 Pin Configuration and Functions D Package 8-Pin SOIC Top View DRB Package 8-Pin VSON Top View Pin Functions PIN NO. I/O DESCRIPTION NAME SOIC VSON Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap BOOT 2 2 I/O capacitor between this pin and the Phase pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. Enable/power good input/output pin with 1-M Ω impedance. Connect this pin to High to enable and Low to disable the device. When disabled, the device EN/PG 7 7 I/O draws less than 350- μA bias current. If the VDD is below UVLO threshold or over temperature shutdown occurs, this pin is internally pulled low. GND 4 4 – Ground pin. All signals are referenced to this node. Lower gate drive sink and source output. Connect to the gate of the low-side LGATE 5 5 O power N-Channel MOSFET. Connect this pin to the source of the upper MOSFET and the drain of the PHASE 8 8 I lower MOSFET. This pin provides a return path for the upper gate driver. The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the 3-state PWM Input section PWM 3 3 I under DETAILED DESCRIPTION for further details. Connect this pin to the PWM output of the controller. Exposed die Thermal pad – Connect directly to the GND for better thermal performance and EMI. pad Upper gate drive sink/source output. Connect to gate of high-side power N- UGATE 1 1 O Channel MOSFET. Connect this pin to a 5-V bias supply. Place a high quality bypass capacitor VDD 6 6 I from this pin to GND. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS28226 |
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同様の説明 - TPS28226DG4 |
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