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LB1876 データシート(PDF) 8 Page - ON Semiconductor |
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LB1876 データシート(HTML) 8 Page - ON Semiconductor |
8 / 12 page LB1876 No.6201-8/12 Continued from preceding page. Pin No. Pin name Function Equivalent curcuit 22 PD Phase comparator output pin. The phase error is converted to a pulse duty and output from this pin. 22 VREG 300 Ω 23 CLD Phase lock signal mask time setting pin. A mask time of about 90ms can be set by inserting a capacitor (about 0.1 μF) between this pin and ground. Leave this pin open if there is no need to mask. 23 VREG 300 Ω 24 FGS FG Schmitt output pin. Open collector output. 24 VREG 25 LD Phase lock detection output pin. Open collector output. Turns on (goes low) when phase lock is detected. 25 VREG 26 S/S Start/stop control pin. Low: 0 to 1.5V High: 3.5V to VREG Hysteresis: About 0.5V Apply a low level to start; this pin goes high when open. 26 VREG 22k Ω 2k Ω 27 CLK Clock input pin. Low: 0 to 1.5V High: 3.5V to VREG Hysteresis: About 0.5 V fCLK = 10kHz maximum If there is noise on the clock signal, remove that noise with a capacitor. 27 VREG 22k Ω 2k Ω 30 VCC Power supply pin Insert a capacitor between this pin and ground to prevent noise from entering the IC. (Use a value of 20 or 30 μF or higher.) Continued on next page. |
同様の部品番号 - LB1876 |
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同様の説明 - LB1876 |
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