Pin Names

Description

D

Data Inputs

CP

Clock Pulse Input

OE

TRI-STATE Output Enable Input

O

TRI-STATE Outputs

Functional Description

The ’ACQ/’ACTQ374 consists of eight edge-triggered

flip-flops with individual D-type inputs and TRI-STATE true

outputs. The buffered clock and buffered Output Enable are

common to all flip-flops. The eight flip-flops will store the

state of their individual D inputs that meet the setup and hold

time requirements on the LOW-to-HIGH Clock (CP) transi-

tion. With the Output Enable (OE) LOW, the contents of the

eight flip-flops are available at the outputs. When the OE is

HIGH, the outputs go to the high impedance state. Operation

of the OE input does not affect the state of the flip-flops.

Truth Table

Inputs

Outputs

D

n

CP

OE

O

n

H

N

LH

L

N

LL

XX

H

Z

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

Logic Diagram

DS100239-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

www.national.com

2