データシートサーチシステム |
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54ACT564L データシート(PDF) 2 Page - National Semiconductor (TI) |
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54ACT564L データシート(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Connection Diagrams Functional Description The’ACT564 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE complement out- puts. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transi- tion. With the Output Enable (OE) LOW, the complement of the contents of the eight flip-flops are available at the out- puts. When OE is HIGH, the outputs go to the high imped- ance state. Operation of the OE input does not affect the state of the flip-flops. Function Table Inputs Internal Outputs Function OE CP D Q O N H H L NC Z Hold H H H NC Z Hold H N L L Z Load H N H H Z Load L N L L H Data Available L N H H L Data Available L H L NC NC No Change in Data L H H NC NC No Change in Data H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition NC = No Change Pin Assignment for DIP, and Flatpak DS100994-3 Pin Assignment for LCC DS100994-4 www.national.com 2 |
同様の部品番号 - 54ACT564L |
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同様の説明 - 54ACT564L |
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