Si3462-EVB

Rev. 1.2

9

After power-up, the STATUS pin of the Si3462 is in a high-impedance state and is used for measuring the voltage

set by the DIP switch and the associated resistor network. Then, during normal operation, this pin drives the status

LED via transistor Q3.

The mode setting voltage steps are provided by a simple 4-bit DAC. Each mode setting resistor should be

connected either to GND or +3.3 V for proper operation. Take care not to short the +3.3 V supply to GND, and

remember to activate the reset button for the new configuration to take effect.

The voltage thresholds found in Table 2 on page 7 take into account the slight loading effect of Q3's base current;

therefore, it is recommended to use the same source resistance (around 2.0 k) as that of the Si3462-EVB

network when providing the status pin voltage from a different voltage source, such as a simple voltage divider or a

DAC. Different resistor values may be used in the mode setting network, but the trade-off between voltage step

accuracy and the additional worst-case supply current should be considered. For high value resistors, the base

current will alter the voltage steps, while low value resistors may place higher loads on the STATUS pin when

driving the LED.

6.2. Detection

The detection process consists of sensing a nominal 25 k signature resistance in parallel with up to 0.15 µF of

capacitance. The signature resistance measurement has to be carried out in the 2.8 to 10 V output voltage range

with a 5 mA current limit.

To eliminate the possibility of false detection events, the Si3462-EVB reference design performs a robust 3-point

detection sequence by varying the voltage across the load and sensing the load current changes. This minimizes

effects, such as those caused by the diode bridges present in powered devices (PDs).

20+20+50 ms at each respective level. If the PD's signature resistance is in the RGOOD range of 17 to 29 k, the

Si3462 proceeds to classification and powerup. If the PD resistance is not in this range, the detection sequence

repeats continuously.

Detection is sequenced approximately every 360 ms until RGOOD is sensed, indicating a valid PD has been

detected. The STATUS LED (D2) is flashed at an approximate rate of 1.5 Hz to indicate that the PSE is searching

for a valid PD.

6.3. Classification

To save bill of materials cost, the Si3462 does not perform classification when configured for 15.4 W of output

power. There is also a pin-programmable mode for no classification and 30 W of output power to support

non-standard PDs. If no classification is done, the classification components of the bill of materials do not need to

be populated. The classification mark components only need to be populated for 30 W mode with classification.

The Si3462 implements both the one-event and two-event physical layer classification methods. For one-event

classification, the pass FET Q4 is turned on and programmed for an output voltage of 18 V with a current limit of

75 mA for 30 ms. For the two-event classification, the 18 V pulse is output twice with an 8.5 V amplitude mark

pulse for 10 ms between the two classification pulses.

If the class level of the PD is not within the supported level as set by the initial voltage on the Si3462's STATUS pin

(refer to the Operating Mode Configuration section above), an error is declared, and the LED blinks rapidly at a rate

of 10 Hz for two seconds before the Si3462 goes back to the detection cycle. This is referred to as

classification-based power denial. If the class level is in the supported range, the Si3462 proceeds to powerup.

This is referred to as classification-based power granting. Classification level is determined according to the

current measured at the ISENSE input as shown in Table 3.