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SI8050AA-B-IU データシート(PDF) 11 Page - Silicon Laboratories |
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SI8050AA-B-IU データシート(HTML) 11 Page - Silicon Laboratories |
11 / 23 page Si80xx Rev. 1.0 11 3.1. Device Startup Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow the states of inputs. 3.2. Undervoltage Lockout Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply. See Figure 5 for more details. Figure 5. Device Behavior during Normal Operation INPUT VDD1 UVLO- VDD2 UVLO+ UVLO- UVLO+ OUTPUT tSTART tSTART tSTART tPHL tPLH tSD |
同様の部品番号 - SI8050AA-B-IU |
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同様の説明 - SI8050AA-B-IU |
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