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ADF5904WCCPZ-RL7 データシート(PDF) 11 Page - Analog Devices |
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ADF5904WCCPZ-RL7 データシート(HTML) 11 Page - Analog Devices |
11 / 15 page Data Sheet ADF5904 DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0 RESERVED RESERVED CONTROL BITS 0 0 0 0 0 0 0 0 0 PC4 PC3 PC2 PC1 PLO LPB DIO 1 0 1 0 0 C2(0) C1(0) 0 REGISTER 0 (R0) PC4 PUP CH4 0 1 POWER DOWN POWER UP PC3 PUP CH3 0 1 POWER DOWN POWER UP PC2 PUP CH2 0 1 POWER DOWN POWER UP PC1 PUP CH1 0 1 POWER DOWN POWER UP PLO PUP LO 0 1 POWER DOWN POWER UP DIO DOUT VSEL 0 1 3.3V 1.8V LPB LO_IN PIN BIAS 0 1 NO DC BIAS 1.5V DC BIAS Figure 18. Register 0 REGISTER 0 Register 0 Control Bits With Bits[C2:C1] set to 00, Register R0 is programmed. Figure 18 shows the input data format for programming this register. DOUT VSEL DB8 controls the DOUT logic levels. Set this bit to 0 to set the DOUT logic level to 3.3 V, and set this bit to 1 to sets the DOUT logic level to 1.8 V. LO_IN Pin Bias DB9 controls the dc bias voltage on the LO_IN pin (Pin 29). Set this bit to 0 to set no dc bias on the LO_IN pin, and set this bit to 1 to set the dc bias to 1.5 V. AC couple the LO signal to the LO_IN pin. PUP LO DB10 provides the power-up bit for the LO block. Set this bit to 0 to power down the LO block, and set this bit to 1 to return the LO block to normal operation. PUP CH1 DB11 provides the power-up bit for RF Receiver Channel 1. Setting this bit to 0 performs a power-down of Channel 1 blocks. Setting this bit to 1 returns Channel 1 blocks to normal operation. PUP CH2 DB12 provides the power-up bit for RF Receiver Channel 2. Set this bit to 0 to power down the Channel 2 blocks, and set this bit to 1 to return the Channel 2 blocks to normal operation. PUP CH3 DB13 provides the power-up bit for RF Receiver Channel 3. Set this bit to 0 to power down the Channel 3 blocks, and set this bit to 1 to return the Channel 3 blocks to normal operation. PUP CH4 DB14 provides the power-up bit for RF Receiver Channel 4. Set this bit to 0 to power down the Channel 4 blocks, and set this bit to 1 to return the Channel 4 blocks to normal operation. Rev. 0 | Page 11 of 15 |
同様の部品番号 - ADF5904WCCPZ-RL7 |
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同様の説明 - ADF5904WCCPZ-RL7 |
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