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SI53102-A3 データシート(PDF) 7 Page - Silicon Laboratories |
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SI53102-A3 データシート(HTML) 7 Page - Silicon Laboratories |
7 / 15 page Si53102-A1/A2/A3 Rev 1.2 7 2. Test and Measurement Setup Figures 1 through 3 show the test load configuration for the differential clock signals. Figure 1. 0.7 V Differential Load Configuration The outputs from this device can also support LVDS, LVPECL, or CML differential signaling levels using alternative termination. For recommendations on how to achieve this, see “AN781: Alternative Output Termination for Si5213x, Si5214x, Si5121x, and Si5315x PCIe Clock Generator and Buffer Families” at www.silabs.com. Figure 2. Differential Measurement for Differential Output Signals (AC Parameters Measurement) M eas ure m ent Po in t 2p F 50 M e as ur em e n t Po in t 2p F 50 L1 L1 = 5 " OU T + OU T - L1 |
同様の部品番号 - SI53102-A3 |
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同様の説明 - SI53102-A3 |
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