CDCM7005_15 datasheet(9/52 Pages) TI1

部品番号	CDCM7005

部品情報	3.3-V High Performance Clock Synchronizer and Jitter Cleaner

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CDCM7005

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SCAS793F – JUNE 2005 – REVISED JULY 2015

Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

LVCMOS input current for PD, RESET,

IIH

HOLD, REF_SEL, PRI_REF, SEC_REF,

VI = VCC, VCC = 3.6 V

5

µA

(see (4))

LVCMOS input current for PD, RESET,

IIL

HOLD, REF_SEL, PRI_REF, SEC_REF,

VI = 0 V, VCC = 3.6 V

–15

–35

µA

(see (4))

VCC = min to max,

VCC–0.1

IOH = –100 μA

High-level output voltage for LVCMOS

VOH

V

outputs

VCC = 3 V, IOH = –6 mA

2.4

VCC = 3 V, IOH = –12 mA

2

VCC = min to max,

0.1

IOL = 100 μA

Low-level output voltage for LVCMOS

VOL

V

outputs

VCC = 3 V, IOL = 6 mA

0.5

VCC = 3 V, IOL = 12 mA

0.8

IOH

High-level output current

VCC = 3.3 V, VO = 1.65 V

–30

mA

IOL

Low-level output current

VCC = 3.3 V, VO = 1.65 V

33

mA

VREF_IN = VCC/2, Y = VCC/2,

tpho

Phase offset (REF_IN to Y output)(5)

1.8

ns

see Figure 11, Load = 10 pF

tsk(p)

LVCMOS pulse skew, see Figure 10

Crosspoint to VCC/2 load, see Figure 12

150

ps

tpd(LH)

Propagation delay from VCXO_IN to Yx,

Crosspoint to VCC/2,

2

2.5

3

ns

see Figure 10

Load = 10 pF, see Figure 12 (PLL bypass mode)

tpd(HL)

All outputs have the same divider ratio

55

LVCMOS single-ended output skew, see (6)

tsk(o)

ps

and Figure 10

Outputs have different divider ratios

70

Duty cycle

LVCMOS

VCC/2 to VCC/2

49%

51%

20% to 80% of swing (load

tslew-rate

Output rise/fall slew rate

2.4

3.5

V/ns

see Figure 12)

LVPECL

fclk

Output frequency, see (3) and Figure 5

Load, see Figure 13

0

1500

MHz

II

LVPECL input current

VI = 0 V or VCC

±20

µA

VCC–0.8

VOH

LVPECL high-level output voltage

Load, See Figure 13

VCC–1.18

V

1

VCC–1.5

VOL

LVPECL low-level output voltage

Load, See Figure 13

VCC–2

V

5

|VOD|

Differential output voltage

See Figure 9 and load, see Figure 13

500

mV

tpho

Phase offset (REF_IN to Y output)(6)

VREF_IN = VCC/2 to cross point of Y, see Figure 11

–200

100

ps

tpd(LH)

Propagation delay time, VCXO_IN to Yx,

Cross point-to-cross point, load

340

490

640

ps

see Figure 10

see Figure 13

tpd(HL)

Cross point-to-cross point, load

tsk(p)

LVPECL pulse skew, see Figure 10

10

ps

see Figure 13

Load see Figure 13, all outputs have the same

20

divider ratio

tsk(o)

LVPECL output skew(6)

ps

Load see Figure 13, outputs have

50

different divider ratios

tr / tf

Rise and fall time

20% to 80% of VOUTPP, see Figure 9

120

170

220

ps

CI

Input capacitance at VCXO_IN, VCXO_IN

1.5

pF

LVCMOS-TO-LVPECL

Output skew between LVCMOS and

Cross point to VCC/2; load,

tsk(P_C)

1.7

2

2.4

ns

LVPECL outputs, see (7) and Figure 10

see Figure 12 and Figure 13

PLL ANALOG LOCK

IOH

High-level output current

VCC = 3.6 V, VO = 1.8 V

–110

µA

IOL

Low-level output current

VCC = 3.6 V, VO = 1.8 V

110

µA

(4)

These inputs have an internal 150-k

Ω pullup resistor.

(5)

This is valid only for the same frequency of REF_IN clock and Y output clock. It can be adjusted by the SPI controller (reference delay M

and VCXO delay N).

(6)

The tsk(o) specification is only valid for equal loading of all outputs.

(7)

The phase of LVCMOS is lagging in reference to the phase of LVPECL.

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