CDCM7005RGZT datasheet(5/52 Pages) TI1

部品番号	CDCM7005RGZT

部品情報	3.3-V High Performance Clock Synchronizer and Jitter Cleaner

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CDCM7005

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SCAS793F – JUNE 2005 – REVISED JULY 2015

Pin Functions (continued)

I/O

DESCRIPTION

NAME

BGA

QFN

This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET

is the default function. This pin is low active and can be activated external or via

the corresponding bit in the SPI register. In case of RESET, the charge pump (CP)

is switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider

settings are maintained in SPI registers). The LVPECL outputs are static low and

high respectively and the LVCMOS outputs are all low or high if inverted. RESET

is not edge triggered and should have a pulse duration of at least 5 ns.

HOLD

H8

14

I

In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is

released and with the next valid reference clock cycle the charge pump is

switched back in to normal operation (CP stays in 3-state as long as no reference

clock is valid). During HOLD, the P divider and all outputs Yx are at normal

operation. This mode allows an external control of the frequency hold-over mode.

The input has an internal 150-k

Ω pullup resistor.

This LVCMOS output can be programmed (SPI) to provide either the

STATUS_VCXO information or serve as current path for the charge pump (CP).

STATUS_VCXO is the default setting.

In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXO

I_REF_CP

D8

22

O

input (frequencies above 2 MHz are interpreted as valid clock; active high).

In case of I_REF_CP, it provides the current path for the external reference

resistor (12 k

Ω ±1%) to support an accurate charge pump current, optional. Do not

use any capacitor across this resistor to prevent noise coupling via this node. If

the internal 12 k

Ω is selected (default setting), this pin can be left open.

LVCMOS input, asynchronous power down (PD) signal. This pin is low active and

can be activated external or by the corresponding bit in the SPI register (in case of

logic high, the SPI setting is valid). Switches the device into power-down mode.

Resets M- and N-Divider, 3-states charge pump, STATUS_REF, or

PD

H1

1

I

PRI_SEC_CLK pin, STATUS_VCXO or I_REF_CP pin, PLL_LOCK pin, VBB pin

and all Yx outputs. Sets the SPI register to default value; has internal 150-k

Ω

pullup resistor. It is recommended to ramp up the PD with the same time as VCC

and AVCC or later. The ramp up rate of the PD should not be faster than the ramp

up rate of VCC and AVCC.

LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in

lock (see feature description). This output can be programmed to be digital lock

detect or analog lock detect (see feature description).

The PLL is locked (set high), if the rising edge either of PRI_REF or SEC_REF

clock and VCXO_IN clock at the phase frequency detector (PFD) are inside the

lock detect window for a predetermined number of successive clock cycles.

PLL_LOCK

A8

25

I/O

The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or

SEC_REF) clock and VCXO_IN clock at the PFD are outside the lock detect

window or if a certain frequency offset between reference frequency and feedback

frequency (VCXO) is detected.

Both, the lock detect window and the number of successive clock cycles are user

definable (via SPI).

LVCMOS input for the primary reference clock, with an internal 150-k

Ω pullup

PRI_REF

A1

36

I

resistor and input hysteresis.

This output can be programmed (SPI) to provide either the STATUS_REF or

PRI_SEC_CLK information. This pin is set high if one of the STATUS conditions is

valid. STATUS_REF is the default setting.

In case of STATUS_REF, the LVCMOS output provides the Status of the

PRI_SEC_CLK

C8

23

O

Reference Clock. If a reference clock with a frequency above 2 MHz is provided to

PRI_REF or SEC_REF STATUS_REF will be set high.

In case of PRI_SEC_CLK, the LVCMOS output indicates whether the primary

clock [high] or the secondary clock [low] is selected.

LVCMOS reference clock selection input. In the manual mode the REF_SEL

signal selects one of the two input clocks:

REF_SEL

A2

35

I

REF_SEL [1]: PRI_REF is selected;

REF_SEL [0]: SEC_REF is selected;

The input has an internal 150-k

Ω pullup resistor.

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