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LMK61A2-125M00SIAT データシート(PDF) 6 Page - Texas Instruments |
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LMK61A2-125M00SIAT データシート(HTML) 6 Page - Texas Instruments |
6 / 23 page LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M SNAS676A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com 6.10 Frequency Tolerance Characteristics (1) VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fT Total Frequency Tolerance All output formats, frequency bands and -50 50 ppm device junction temperature up to 125°C; includes initial freq tolerance, temperature & supply voltage variation, solder reflow and aging (10 years) (1) Ensured by characterization. 6.11 Power-On/Reset Characteristics (VDD) VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VTHRESH Threshold Voltage(1) 2.72 2.95 V VDROOP Allowable Voltage Droop(2) 0.1 V tSTARTUP Startup Time (1) Time elapsed from VDD at 3.135 V to output 10 ms enabled tOE-EN Output enable time(2) Time elapsed from OE at VIH to output enabled 50 us tOE-DIS Output disable time(2) Time elapsed from OE at VIL to output disabled 50 us (1) Ensured by characterization. (2) Ensured by design. 6.12 PSRR Characteristics (1) VDD = 3.3 V, TA = 25°C, FS[1:0] = NC, NC PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PSRR Spurs Induced by 50 mV Sine wave at 50 kHz -70 dBc Power Supply Ripple(2)(3) at Sine wave at 100 kHz -70 156.25 MHz output, all Sine wave at 500 kHz -70 output types Sine wave at 1 MHz -70 (1) Refer to Parameter Measurement Information for relevant test conditions. (2) Measured max spur level with 50 mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin (3) DJSPUR (ps, pk-pk) = [2*10(SPUR/20) / (π*fOUT)]*1e6, where PSRR or SPUR in dBc and fOUT in MHz. 6.13 PLL Clock Output Jitter Characteristics (1) (2) VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RJ RMS Phase Jitter(3) fOUT ≥ 100 MHz, Integer-N PLL, All output 100 200 fs RMS (12 kHz – 20 MHz) types (1 kHz – 5 MHz) (1) Refer to Parameter Measurement Information for relevant test conditions. (2) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer). (3) Ensured by characterization. 6.14 Typical 156.25 MHz Output Phase Noise Characteristics (1) (2) VDD = 3.3 V, TA = 25°C, Output Type = LVPECL/LVDS/HCSL SYMBOL PARAMETER OUTPUT TYPE UNITS LVPECL LVDS HCSL phn10k Phase noise at 10 kHz offset -143 -143 -143 dBc/Hz Phn20k Phase noise at 20 kHz offset -143 -143 -143 dBc/Hz phn100k Phase noise at 100 kHz offset -144 -144 -144 dBc/Hz Phn200k Phase noise at 200 kHz offset -145 -145 -145 dBc/Hz (1) Refer to Parameter Measurement Information for relevant test conditions. (2) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer). 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-100M LMK61A2- 125M LMK61A2-156M LMK61A2-312M LMK61I2-100M |
同様の部品番号 - LMK61A2-125M00SIAT |
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同様の説明 - LMK61A2-125M00SIAT |
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