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SI4704-D60 データシート(PDF) 7 Page - Silicon Laboratories |
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SI4704-D60 データシート(HTML) 7 Page - Silicon Laboratories |
7 / 39 page Si4704/05-D60 Rev. 1.2 7 Figure 1. Reset Timing Parameters for Busmode Select Table 3. Reset Timing Characteristics1,2,3 (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Min Typ Max Unit RST Pulse Width and GPO1, GPO2/INT Setup to RST tSRST 100 — — µs GPO1, GPO2/INT Hold from RST tHRST 30 — — ns RST Pulse Release Time Before VDD/VIO Turn Off tRRST 30 — — ns Important Notes: 1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST. 2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 3. When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. 4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and GPO2 low. 5. RST must be held low for at least 100 µs after all voltage supplies have been ramped up. 6. RST needs to be asserted (pulled low) prior to any supply voltage is ramped down. |
同様の部品番号 - SI4704-D60 |
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同様の説明 - SI4704-D60 |
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