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SI4707-B20 データシート(PDF) 6 Page - Silicon Laboratories

部品番号 SI4707-B20
部品情報  WEATHER BAND AND SAME DATA RECEIVER
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メーカー  SILABS [Silicon Laboratories]
ホームページ  http://www.silabs.com
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SI4707-B20 データシート(HTML) 6 Page - Silicon Laboratories

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Si4707-B20
6
Rev. 0.8
Figure 1. Reset Timing Parameters for Busmode Select
Table 4. Reset Timing Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Unit
RST Pulse Width and GPO1, GPO2/INT Setup to RST
tSRST
100
µs
GPO1, GPO2/INT Hold from RST
tHRST
30
ns
Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
GPO2 low.
70%
30%
GPO1
70%
30%
GPO2/
INT
70%
30%
tSRST
RST
tHRST


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