データシートサーチシステム |
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TS3002 データシート(PDF) 3 Page - Silicon Laboratories |
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TS3002 データシート(HTML) 3 Page - Silicon Laboratories |
3 / 13 page TS3002 TS3002 Rev. 1.0 Page 3 ELECTRICAL CHARACTERISTICS VDD = 1V, VCNTRL = VDD, VBOOST = 0V, RSET = 4.32MΩ, CSET = 7.9pF, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF, CLOAD(PWM) = 0pF unless otherwise noted. Values are at TA = 25°C unless otherwise noted. See Note 1. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDD 0.9 1 1.8 V Supply Current IDD 1 1.5 µA -40°C ≤ T A ≤ 85°C 2.8 VCNTRL = 0.15 x VDD 2.1 3.7 -40°C ≤ T A ≤ 85°C 5.4 VBOOST = VDD 2.16 3.2 -40°C ≤ T A ≤ 85°C 4.8 VBOOST = VDD, VCNTRL = 0.15 x VDD 3.6 5.3 -40°C ≤ T A ≤ 85°C 7.3 FOUT Period tFOUT 37 40.6 44 µs -40°C ≤ T A ≤ 85°C 34.7 45.6 VBOOST = VDD 36 39.5 43 -40°C ≤ T A ≤ 85°C 33 48 FOUT Period Line Regulation ∆t FOUT/V 1V ≤ V DD ≤ 1.8V 1.3 %/V VBOOST = VDD -1.6 FOUT Period Temperature Coefficient ∆t FOUT/∆T 0.044 %/°C VBOOST = VDD 0.086 PWMOUT Duty Cycle DC(PWMOUT) VCNTRL = 0.03 x VDD 4.5 8.9 13 % VCNTRL = 0.15 x VDD 44 49.3 54 VCNTRL = 0.27 x VDD 83 90.5 97 VCNTRL = 0.03 x VDD VBOOST = VDD 4.5 8.5 12.5 VCNTRL = 0.15 x VDD 47 50.4 54 VCNTRL = 0.27 x VDD 86 91.2 96 FOUT, PWMOUT Rise Time tRISE See Note 2, CL = 15pF 8.6 ns FOUT, PWMOUT Fall Time tFALL See Note 2, CL = 15pF 7.9 ns FOUT Jitter See Note 3 0.08 % RSET Pin Voltage V(RSET) 0.3 V CNTRL Output Current ICNTRL 25 45 nA -40°C ≤ T A ≤ 85°C 80 PWMOUT Enable VPWM_EN (VDD - VCNTRL ), 0.9V < VDD < 1.8V 375 mV PWMOUT Disable VPWM_DIS (VDD - VCNTRL ), 0.9V < VDD < 1.8V 131 mV BOOST Enable VIH (VDD – VBOOST ), 0.9V < VDD < 1.8V 77 mV BOOST Disable VIL 0.9V < VDD < 1.8V 77 mV BOOST Input Current IBOOST 10 nA High Level Output Voltage, FOUT and PWMOUT VDD - VOH IOH = 1mA 160 mV Low-level Output Voltage, FOUT and PWMOUT VOL IOL = 1mA 140 mV Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified. Note 2: Output rise and fall times are measured between the 10% and 90% of the VDD power-supply voltage levels. The specification is based on lab bench characterization and is not tested in production. Note 3: Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench characterization and is not tested in production. |
同様の部品番号 - TS3002 |
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同様の説明 - TS3002 |
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