データシートサーチシステム |
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TPL5111 データシート(PDF) 6 Page - Texas Instruments |
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TPL5111 データシート(HTML) 6 Page - Texas Instruments |
6 / 25 page EN/ONE_SHOT VDD DONE DRV ttIPt ttDDONEt tDONE trDRV tfDRV DELAY/M_RST ttM_DRVt tR_EXT ttIPt ttDRVnt ttDRVn + tDBt TPL5111 SNAS659A – JUNE 2015 – REVISED JULY 2015 www.ti.com 6.6 Timing Requirements MIN(1) NOM(2) MAX(1) UNIT trDRVn Rise Time DRVn(3) Capacitive load 50 pF 50 ns tfDRVn Fall Time DRVn(3) Capacitive load 50 pF 50 ns Min delay(4) 100 ns tDDONE DONE to DRVn delay Max delay (4) tDRVn tM_DRV Valid manual MOSFET Power ON Observation time 30ms 20 ms De-bounce manual MOSFET Power tDB 20 ms ON (1) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method. (2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. (3) This parameter is specified by design and/or characterization and is not tested in production. (4) from DRVn rising edge. Figure 1. TPL5111 Timing 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5111 |
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